Stacked Semiconductor Die Structure for ESD-Safe Bonding
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Solution Overview
Problem
Semiconductor devices are prone to damage due to electro-static discharge (ESD) during fabrication, leading to decreased yields in semiconductor production.
Innovation Solution
The implementation of an anti-arcing material layer, typically a metallic layer such as titanium, is used to cover the semiconductor dies and bonding structures, which helps in minimizing charge accumulation and discharging, thereby protecting the devices from ESD during bonding and de-bonding processes. This is achieved through a process involving the deposition of the anti-arcing material layer and subsequent encapsulation with an insulating material, ensuring the layer is in contact with the semiconductor dies and bonding structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor devices are fabricated using conventional processes without anti-arcing protection, then manufacturing complexity is reduced, but the devices are damaged by electro-static discharge (ESD) during bonding and de-bonding processes
Solution Approach 1:
An anti-arcing material layer is deposited over the semiconductor devices before bonding operations. This preliminary protective layer prevents charge accumulation and ESD damage during subsequent bonding and de-bonding processes, thereby improving device reliability without significantly complicating the fabrication process
Solution Approach 2:
The anti-arcing material layer acts as an intermediary protective barrier between the semiconductor devices and the harmful electro-static discharge. This intermediate layer absorbs or dissipates charges that would otherwise damage the devices during bonding operations, resolving the contradiction between maintaining simple processes and ensuring device reliability
2Reliability
If anti-arcing material layer is deposited over semiconductor devices, then ESD damage is prevented, but manufacturing process complexity increases
Solution Approach 1:
The patent modifies the fabrication process by adding a deposition step for the anti-arcing material layer. This parameter change in the manufacturing process (adding a protective layer) improves device reliability by preventing ESD damage, while the added process step is a straightforward deposition operation that minimizes impact on overall manufacturing ease
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The anti-arcing layers effectively reduce the risk of damage from ESD, enhancing the reliability and yield of semiconductor devices by preventing arcing and charge accumulation during critical fabrication steps.
Implementation Method 1
In semiconductor fabrication, charges may be accumulated and cause electro-static discharge (ESD). Accordingly, semiconductor devices may be damaged due to ESD
Implementation Method 2
an anti-arcing material layer is formed to cover a top tier semiconductor die, sidewalls of the top tier semiconductor die, and a back surface of the top tier semiconductor die
Data Source
AI summary
A device die including a first semiconductor die, a second semiconductor die, an anti-arcing layer and a first insulating encapsulant is provided. The second semiconductor die is stacked over and electrically connected to the first semiconductor die. The anti-arcing layer is in contact with the second semiconductor die. The first insulating encapsulant is disposed over the first semiconductor die and laterally encapsulates the second semiconductor die. Furthermore, methods for fabricating device dies are provided.