3D Stacked Die Package with Floor Connectivity Die
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Solution Overview
Problem
Conventional stacked-die assemblies in microelectronics packages result in thick semiconductor substrates that are not useful for signal processing, leading to increased package thickness and packaging costs, which do not meet the low-profile requirements of modern portable products.
Innovation Solution
A three-dimensional (3D) package design with vertically stacked dies using a multilayer laminate and mold device regions, where the first mold compound encapsulates the first device die and floor interconnections, and the second mold compound encapsulates the second device die, with exposed interconnections for electrical connection, reducing the need for expensive photolithography/etching/plating steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional stacked-die assemblies use thick semiconductor substrates for mechanical stability, then the package thickness increases, but this does not meet low-profile requirements for modern portable products
Solution Approach 1:
The invention divides the substrate function into two separate components: a thin semiconductor die for signal processing and a separate laminate substrate for mechanical support. This segmentation allows the semiconductor die to be thinned to minimal thickness while the laminate substrate provides the necessary mechanical stability, thereby resolving the contradiction between reduced package thickness and maintained mechanical strength.
Solution Approach 2:
The invention transitions from a conventional single-substrate architecture to a vertically stacked three-dimensional architecture where the semiconductor die is mounted on top of the laminate substrate. This dimensional change enables the semiconductor die to be extremely thin while the overall package thickness is controlled by the laminate substrate thickness, achieving low-profile requirements without sacrificing mechanical stability.
2Reliability
If conventional stacked-die assemblies use photolithography/etching/plating steps for interconnection, then electrical connectivity is achieved, but packaging cost significantly increases
Solution Approach 1:
The invention extracts the interconnection formation process from the semiconductor fabrication sequence and relocates it to the packaging stage. Instead of forming interconnections through expensive photolithography/etching/plating steps during semiconductor manufacturing, the invention uses simple wire bonding or flip-chip techniques during packaging, significantly reducing manufacturing cost while maintaining electrical connectivity reliability.
Solution Approach 2:
The invention performs preliminary preparation of interconnection structures on the laminate substrate before mounting the semiconductor die. By pre-forming pad structures and conductive traces on the laminate substrate in advance, the actual interconnection process during packaging is simplified and accelerated, reducing both cost and complexity while ensuring reliable electrical connectivity.
Data Source
AI summary
The present disclosure describes a process for making a three-dimensional (3D) package, which starts with providing a mold precursor module that includes a first device die and a floor connectivity die (FCD) encapsulated by a mold compound. The FCD includes a sacrificial die body and multiple floor interconnections underneath the sacrificial die body. Next, the mold compound is thinned down until the sacrificial die body of the FCD is completely consumed, such that each floor interconnection is exposed through the mold compound. The thinning down step does not affect a device layer in the first device die. A second device die, which includes a die body and multiple electrical die interconnections, is then mounted over the exposed floor interconnections. Herein, each electrical die interconnection is vertically aligned with and electrically connected to a corresponding floor interconnection from the FCD.