Stacked Die Ground Shield for Noise Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In stacked semiconductor devices, noise interference from one chip can disrupt sensitive components like microcontrollers when they are arranged in a stacked configuration with power transistors or noisy dies.
Innovation Solution
A ground shield is created by depositing an oxide layer on the back of the noisy die and a metal layer on top of it, which is then bonded to a lead frame and connected to a voltage source, providing a shielding voltage to isolate noise from the sensitive controller die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chips are stacked in a single device, then device integration and compactness are improved, but noise interference between chips increases
Solution Approach 1:
A ground shield layer is introduced as an intermediary between the power transistor die and the controller die. This ground shield acts as a mediator that blocks electromagnetic noise and interference from the power transistor die from reaching the controller die, while allowing both dies to maintain their stacked configuration for compact integration.
2Object-affected harmful factors
If a ground shield is added between stacked dies, then noise immunity is improved, but device complexity increases
Solution Approach 1:
The ground shield is merged with the existing packaging structure by forming it as part of the interconnect substrate or lead frame. This integration approach combines the shielding function with the existing mechanical support and electrical interconnection structure, avoiding the need for separate shielding components and minimizing additional complexity.
3Area of stationary object
If chips are stacked in flip-chip fashion, then space utilization is improved, but noise coupling between dies increases
Solution Approach 1:
The ground shield extends in the vertical dimension between the stacked dies, creating a three-dimensional shielding structure. This vertical placement in the z-dimension effectively blocks noise coupling paths between the front-facing surfaces of the stacked dies while maintaining their compact horizontal footprint for efficient space utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces noise interference between stacked dies, enhancing noise immunity in multi-chip modules while maintaining a low-cost stacking arrangement.
Implementation Method 1
depositing a layer of oxide & metal on the back of the wafer may create a voltage shield to keep noise out of the controller die
Data Source
AI summary
The present disclosure relates to semiconductor devices. Embodiments of the teachings thereof may include processes for manufacturing of semiconductor devices and the devices themselves. For example, some embodiments may include an integrated circuit package comprising: a lead frame; a first die mounted on the lead frame in flip-chip fashion, with a frontside of the first die connected to the lead frame; wherein the first die comprises an oxide layer deposited on a backside of the first die and a back metal layer deposited on the oxide layer; and a second die mounted on the back metal layer of the first die.