Stacked Die Package Structure With Exposed Heat Dissipation Layer

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Solution Overview

Problem

The heat dissipation performance of package structures in stacked die packaging is poor due to long heat dissipation paths and low thermal conductivity of the substrate, leading to inefficient heat dissipation.

Innovation Solution

A package structure with a heat dissipation layer disposed on the chip stack and a molding layer in contact with the heat dissipation layer, where the molding layer and heat dissipation layer are coplanar, and the thermal conductivity of the molding layer is less than that of the heat dissipation layer, allowing heat to be directed primarily toward the heat dissipation layer for dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If stacked die packaging technology is used to reduce package size, then integration density is improved, but heat dissipation performance deteriorates

Engineering Contradiction:
Improvepackage sizeVSAvoidheat dissipation performance
Core Design Contradiction:
Volume of moving objectVSTemperature

Solution Approach 1:

The patent transitions from traditional planar packaging to three-dimensional stacked die packaging, arranging multiple chips vertically in different layers. This dimensional change increases integration density while the patent simultaneously addresses heat dissipation by conducting heat primarily in the vertical direction through high-thermal-conductivity materials in the stacking direction, resolving the thermal contradiction inherent in 3D packaging.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent applies different thermal conductivity requirements to different spatial directions and regions. High-thermal-conductivity materials are specifically applied in the vertical stacking direction where heat generation is concentrated, while other regions may use different materials optimized for their specific functions. This localized quality approach allows efficient heat dissipation from hot spots without compromising overall package miniaturization.

Inventive Principle:
Principle #3Local quality

2Temperature

If heat dissipation layer is exposed to environment for better heat dissipation, then heat dissipation performance is improved, but package structure complexity increases

Engineering Contradiction:
Improveheat dissipation performanceVSAvoidpackage structure complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The heat dissipation layer serves multiple functions: it acts as both a thermal management component for heat dissipation and as a structural element integrated into the package architecture. The same layer that dissipates heat also provides mechanical support and defines the package's external profile, eliminating the need for separate heat sink structures and reducing overall package complexity despite improved thermal performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves heat dissipation performance by exposing the heat dissipation layer to the environment and maintaining a compact structure, reducing the package height, and facilitating efficient heat transfer without increasing the overall size.

Implementation Method 1

a thermal conductivity coefficient of the molding layer is less than a thermal conductivity coefficient of the heat dissipation layer

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20260068664A1Package structure and method for manufacturing same, and electronic device
Publication Date: 2026.03.05 RUILI INTEGRATED CIRCUIT CO LTD
  • US20260068664A1 patent drawing
  • US20260068664A1 patent drawing
  • US20260068664A1 patent drawing

AI summary

A package structure and a method for manufacturing the same, and an electronic device are provided. The package structure includes a substrate, a chip stack, a heat dissipation layer, and a molding layer. The chip stack is disposed on the substrate, the heat dissipation layer is disposed on the chip stack, and the molding layer is disposed on the substrate and covers the chip stack. The molding layer is in contact with the heat dissipation layer, the molding layer and the heat dissipation layer are coplanar, and the thermal conductivity coefficient of the plastic encapsulating layer is less than the thermal conductivity coefficient of the heat dissipation layer.