Stacked-Die Microelectronic Package With Inboard Die Nesting

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Solution Overview

Problem

Existing microelectronic device packages have large footprints due to the need for sufficient clearance and separation of wirebonds, which limits their miniaturization and increases the risk of electromagnetic interference and manufacturing voids.

Innovation Solution

The solution involves a stacked-die microelectronic package design where the second die is positioned inboard of the first die, with shorter wirebonds and a unique adhesive structure that encapsulates the second die and wirebonds, allowing for flexible bond site layouts and reduced electromagnetic interference, and using a film-over-wire adhesive to minimize footprint and enhance structural integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wirebonds are arranged with sufficient clearance and separation, then electromagnetic interference is reduced and manufacturing reliability is improved, but package footprint increases

Engineering Contradiction:
Improvemanufacturing reliabilityVSAvoidpackage footprint
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar wirebond arrangement to a three-dimensional configuration by positioning the second die inboard of the first die and routing wirebonds through vertical and lateral pathways. This dimensional change allows wirebonds to achieve sufficient separation and clearance without increasing the package footprint, as the separation is achieved in the vertical dimension rather than requiring larger lateral spacing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nesting by positioning the second die inboard of the first die, with the second die having a smaller footprint that fits within the boundary of the first die. This nested arrangement allows wirebonds from both dies to be routed through overlapping or adjacent pathways without requiring additional lateral space, thereby maintaining compact footprint while ensuring adequate wirebond separation.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If wirebonds have large loop height for sufficient clearance, then package functionality is ensured, but package height increases

Engineering Contradiction:
Improvepackage functionalityVSAvoidpackage height
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent reduces package height by changing the wirebond geometry from high loop-height arcs to flatter, more direct pathways. The wirebonds are routed to bond sites on the inboard surface of each die, creating shorter, lower-loop connections that achieve the necessary clearance through three-dimensional routing rather than requiring large vertical excursions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent inverts the traditional wirebond approach by bonding to the inboard surface of each die rather than the outboard surface. This inversion allows wirebonds to be routed through the encapsulant material in a more direct path, reducing loop height and package height while maintaining sufficient clearance between wirebonds from different dies.

Inventive Principle:
Principle #13The other way round (Inversion)

3Object-affected harmful factors

If terminals have large separation for proper function, then electromagnetic interference is reduced, but package footprint increases

Engineering Contradiction:
Improveelectromagnetic interferenceVSAvoidpackage footprint
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent addresses terminal separation by utilizing three-dimensional routing of wirebonds and traces through the encapsulant material. Terminals can be positioned closer together on the substrate surface, but sufficient electromagnetic separation is achieved by routing connections through different vertical levels and lateral pathways, effectively separating signal paths in the third dimension rather than requiring large lateral spacing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8923004B2Microelectronic packages with small footprints and associated methods of manufacturing
Publication Date: 2014.12.30 MICRON TECHNOLOGY INC
  • US8923004B2 patent drawing
  • US8923004B2 patent drawing
  • US8923004B2 patent drawing

AI summary

Several embodiments of stacked-die microelectronic packages with small footprints and associated methods of manufacturing are disclosed herein. In one embodiment, the package includes a substrate, a first die carried by the substrate, and a second die between the first die and the substrate. The first die has a first footprint, and the second die has a second footprint that is smaller than the first footprint of the first die. The package further includes an adhesive having a first portion adjacent to a second portion. The first portion is between the first die and the second die, and the second portion being between the first die and the substrate.