Stacked Semiconductor Package Interconnects for Uniform Die Signal Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor package structures face challenges in accelerating signal transmission speed due to longer signal paths and increased resistance in 3D-ICs, particularly in high bandwidth memory (HBM) designs with stacked DRAM dies.
Innovation Solution
The semiconductor package structure incorporates a stack structure with varying numbers and sizes of connection structures connecting different dies, optimizing signal transmission paths by adjusting the number and size of connection structures based on the distance from the logic die, thereby reducing overall resistance and improving signal speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D-ICs with stacked dies are used to achieve miniaturization and high density, then integration density is improved, but signal transmission speed deteriorates due to longer signal paths and increased resistance
Solution Approach 1:
The patent applies local quality by varying the number and size of connection structures for different dies based on their specific positions and signal transmission needs. Dies farther from the logic die have more or larger connection structures to compensate for increased resistance, while closer dies have fewer or smaller connections. This localized optimization resolves the contradiction by maintaining signal speed despite increased integration density.
Solution Approach 2:
The patent changes parameters (number and size of connection structures) dynamically based on die position. By adjusting these parameters according to distance from the logic die, the system compensates for resistance variations and maintains consistent signal transmission speed across all dies, thereby resolving the contradiction between high integration density and signal speed.
2Device complexity
If uniform connection structures are used for all dies, then manufacturing complexity is reduced, but signal transmission speed deteriorates due to resistance differences across different dies
Solution Approach 1:
Instead of uniform connection structures, the patent implements local quality by configuring different numbers and sizes of connection structures for different dies based on their positions. This localized differentiation compensates for resistance variations caused by different distances from the logic die, maintaining signal speed while accepting increased manufacturing complexity.
3Speed
If more connection structures are added to compensate for resistance in distant dies, then signal transmission speed is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by selectively adding more or larger connection structures only to dies that require compensation due to their distance from the logic die. Dies closer to the logic die maintain fewer or smaller connection structures. This targeted approach improves signal speed where needed while minimizing overall device complexity.
Data Source
AI summary
The present application discloses a semiconductor package structure and a manufacturing method thereof, and a memory system. The semiconductor package structure includes: a stack structure including a plurality of first dies stacked sequentially along a first direction, wherein the stack structure has a first surface and a second surface opposite to each other along the first direction; and a plurality of first connection structures extending along the first direction from the second surface and respectively connected to different ones of the first dies, wherein the number of the first connection structures connected to different ones of the first dies is different, and/or maximum sizes, along a second direction, of the first connection structures connected to different ones of the first dies are different, and the first direction intersects with the second direction.