Stacked Semiconductor Die Interconnect Through Encapsulant
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Solution Overview
Problem
Conventional semiconductor devices with stacked die configurations face challenges in achieving high-density packaging with reduced manufacturing time and cost due to the complexity of bond wire formation and encapsulant thickness requirements, which increases the package profile and manufacturing expenses.
Innovation Solution
A method of forming a stacked-die semiconductor package with an interconnect structure through an encapsulant to electrically couple the stacked die to a common surface, allowing for simplified accessibility of input and output signals from a single surface, and using multiple substrates with conductive vias and bumps to provide electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bond wires are formed to electrically connect stacked die to substrate, then electrical connectivity is achieved, but package height increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical interconnection through conductive vias and bumps. The interconnect structure extends through the encapsulant in the vertical dimension, allowing electrical connections without increasing lateral package dimensions. This dimensional change eliminates the need for bond wires while achieving the same electrical connectivity function.
Solution Approach 2:
The patent extracts and eliminates the bond wire component from the package structure. By using conductive vias formed through the encapsulant and conductive bumps on die surfaces, the function previously performed by bond wires is achieved through a different mechanism that reduces manufacturing steps and complexity.
2Reliability
If encapsulant thickness is increased to accommodate bond wires, then wire clearance is achieved, but package profile increases and manufacturing cost increases
Solution Approach 1:
The patent eliminates the need for vertical wire routing by forming conductive vias through the encapsulant that provide direct vertical interconnection paths. This allows the encapsulant to be thinner since it no longer needs to accommodate the arching path of bond wires, thereby reducing package profile while maintaining electrical clearance.
3Reliability
If individual encapsulant deposition is performed over each die, then complete coverage is achieved, but manufacturing time and cost increase
Solution Approach 1:
The patent merges the encapsulation process into a single bulk deposition step that covers multiple stacked die simultaneously. Instead of performing separate encapsulant deposition operations over each die, the process applies encapsulant material to the entire stacked structure in one operation, reducing manufacturing steps and improving productivity while maintaining complete coverage.
4Area of stationary object
If stacked die configuration is used to reduce footprint, then area efficiency is improved, but interconnect complexity increases
Solution Approach 1:
The patent resolves the interconnect complexity issue by transitioning from lateral wire bonding to vertical through-encapsulant vias. The conductive vias provide direct vertical pathways through the encapsulant, simplifying the interconnection architecture compared to traditional bond wire routing. This vertical interconnection approach maintains the compact stacked configuration while reducing interconnect complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density semiconductor packages with reduced footprint and manufacturing complexity, lowering costs and improving efficiency by eliminating the need for individual encapsulant deposition over each die and simplifying the interconnect structure.
Implementation Method 1
depositing an encapsulant over the first substrate
Implementation Method 2
forming an interconnect structure through the encapsulant to electrically couple the first and second semiconductor die to a common surface
Data Source
AI summary
A semiconductor device has a first conductive layer formed over a first substrate. A second conductive layer is formed over a second substrate. A first semiconductor die is mounted to the first substrate and electrically connected to the first conductive layer. A second semiconductor die is mounted to the second substrate and electrically connected to the second conductive layer. The first semiconductor die is mounted over the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and the first and second substrates. A conductive interconnect structure is formed through the encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device. Forming the conductive interconnect structure includes forming a plurality of conductive vias through the encapsulant and the first substrate outside a footprint of the first and second semiconductor die.