Stacked IC Die Interconnection Without Silicon Vias
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Solution Overview
Problem
Conventional stacked die packages face challenges in reducing z-height and increasing electrical performance due to limitations in wire bond and Thru Silicon Via (TSV) technologies, which also incur high manufacturing costs and inefficient silicon utilization.
Innovation Solution
The proposed solution involves interconnecting integrated circuit (IC) dies using a method that eliminates the need for silicon vias, allowing for shorter wires and reduced z-height, while utilizing existing wire bond equipment to reduce costs and improve thermal performance by exposing the top side of the die for heat transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bond technology is used to form stacked die packages, then electrical connections can be established between dies, but the package z-height increases due to substrate and over mold layers
Solution Approach 1:
The patent extracts and eliminates the substrate and over mold layers from the package structure. By directly bonding dies to each other without these intermediate layers, the patent reduces the package z-height while maintaining electrical connections between dies through direct die-to-die bonding interfaces.
Solution Approach 2:
The patent transitions from a conventional wire bond approach requiring vertical space for wires and molding to a direct bonding approach that utilizes the horizontal bonding interface between dies. This dimensional shift eliminates the need for over mold and reduces z-height by flattening the package structure.
2Speed
If Thru Silicon Via (TSV) technology is used to form stacked die packages, then high speed electrical performance can be achieved, but manufacturing costs increase and silicon space is consumed
Solution Approach 1:
The patent replaces expensive TSV technology with a more economical direct bonding approach. By eliminating the need for complex via formation processes and expensive equipment, the patent achieves comparable electrical performance at lower manufacturing costs, making the solution more economically viable for high die count packages.
Solution Approach 2:
The patent extracts and eliminates the TSV structure from the die design. By removing the need for silicon via formation, the patent frees up valuable silicon real estate and reduces manufacturing complexity and costs while maintaining high-speed electrical performance through direct die bonding.
3Speed
If TSV technology is used to form high die count stacked die packages, then high speed performance can be achieved, but package z-height reduction remains difficult
Solution Approach 1:
The patent extracts the TSV structure and replaces it with direct die bonding. This elimination of intermediate via structures and the associated molding requirements enables significant z-height reduction while maintaining the high-speed electrical performance needed for modern electronic applications.
4Reliability
If conventional stacked die packages with over molding are used, then wire bonds can be protected, but thermal performance deteriorates due to reduced heat transfer capability
Solution Approach 1:
The patent extracts and eliminates the over mold layer from the package structure. By removing this thermal barrier, the patent enables direct exposure of die surfaces for heat transfer, significantly improving thermal performance while wire bonds are protected through alternative means such as direct die bonding interfaces.
Data Source
AI summary
Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.