Substrate-Less Stacked Die Package for Shorter Interconnect Paths
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Solution Overview
Problem
Conventional semiconductor packaging methods using through-silicon vias (TSVs) and wire bonding face challenges such as increased complexity, cost, limited thermal management, signal speed degradation, and inflexibility, which hinder high-capacity and high-performance applications.
Innovation Solution
A stacked die substrate-less semiconductor package design with a shingled die arrangement and encapsulating casing, featuring a redistribution circuit that connects to interconnect structures, allowing for efficient space utilization, improved thermal dissipation, and scalable die stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) and wire bonding are used for die stacking, then electrical interconnection between dies is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the carrier substrate from the traditional TSV packaging structure, creating a substrate-less design where dies are directly stacked and interconnected. This removal of the intermediate substrate simplifies the overall device structure while maintaining electrical interconnection functionality through direct die-to-die bonding and TSV integration.
Solution Approach 2:
The patent merges multiple functions into the die stack itself: electrical interconnection, mechanical support, and thermal management are all integrated directly into the stacked die structure without requiring a separate carrier substrate. This consolidation reduces device complexity while achieving the same interconnection reliability.
2Temperature
If conventional substrate-based packaging is used, then thermal management is provided, but thermal conductance is limited and thermal dissipation efficiency is reduced
Solution Approach 1:
The patent removes the thermal bottleneck created by the carrier substrate interface, allowing heat to dissipate more efficiently through direct thermal pathways between stacked dies. By eliminating the substrate layer, thermal resistance is reduced and heat transfer efficiency is improved.
Solution Approach 2:
The patent transitions from planar heat dissipation in substrate-based packaging to three-dimensional thermal management in the stacked die configuration. Heat can now dissipate through multiple vertical pathways between closely-spaced dies, significantly improving thermal conductance and dissipation efficiency.
3Reliability
If longer interconnect lengths are used in substrate-based packaging, then electrical connection is achieved, but signal speed degrades
Solution Approach 1:
The patent eliminates the long interconnect paths through the carrier substrate by removing the substrate itself. Electrical signals now travel through direct vertical TSV pathways between adjacent dies, dramatically reducing interconnect length and signal transit time while maintaining reliable electrical connection.
4Strength
If substrate-based packaging is used, then mechanical support is provided, but adaptability and scalability for different die configurations are limited
Solution Approach 1:
The patent creates a dynamic and flexible die stacking architecture where dies can be configured in various arrangements (e.g., different stack heights, lateral offsets, and bonding configurations) without being constrained by a fixed substrate layout. This enables adaptable scaling and reconfiguration for different application requirements while maintaining mechanical integrity through direct die-to-die bonding.
Data Source
AI summary
Implementations described herein relate to various semiconductor device assemblies. In some implementations, an apparatus includes a first integrated circuit die conjoined with a second integrated circuit die in a stack of integrated circuit dies, where the first integrated circuit die includes an end region that extends beyond an edge of the second integrated circuit die. The apparatus includes an interconnect structure that is conjoined with the end region and is electrically coupled to integrated circuitry of the first integrated circuit die and a casing that encapsulates at least a portion of the interconnect structure, at least a portion of the first integrated circuit die, and at least a portion of the second integrated circuit die. The apparatus includes an electrical trace that is conjoined with a surface of the casing, is disposed along a contour of the casing, and is electrically coupled to the interconnect structure.