Stacked Die Interdie Communication via Switching Fabric Reuse
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Solution Overview
Problem
Existing parallel processing systems face limitations in enabling low-latency communication between a large number of tiles in a stacked integrated circuit device, as there is a limit to the number of tiles that can be manufactured on a single die, and current methods require duplication of switching fabric hardware for interdie communication.
Innovation Solution
A stacked integrated circuit device is designed with two dies, each comprising a plurality of processors and a switching fabric, where processors on one die can send data to processors on another die using interdie data connection wires and output exchange buses, reusing the same switching fabric mechanism for both intradie and interdie communication, thereby avoiding duplication of switching fabric hardware and enabling low-latency communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of tiles on a single die is increased to enable more parallel processing, then the parallelism capability is improved, but the manufacturing limit of a single die is reached
Solution Approach 1:
The patent transitions from a two-dimensional arrangement of tiles on a single die to a three-dimensional stacked architecture with multiple dies connected vertically. This dimensional change allows the system to scale beyond the manufacturing limits of single-die tile counts while maintaining low-latency communication through direct vertical interconnects between corresponding tiles on adjacent dies.
Solution Approach 2:
The patent divides the large-scale parallel processing system into multiple separate dies, each containing a manageable number of tiles. This segmentation allows each die to be manufactured within existing fabrication capabilities while the stacked configuration enables the overall system to achieve the desired level of parallelism across multiple dies.
2Ease of operation
If separate switching fabric hardware is provided for interdie communication, then the communication capability between dies is improved, but the hardware duplication increases
Solution Approach 1:
The patent designs the switching fabric on each die to serve dual purposes: handling intradie communication between tiles on the same die and handling interdie communication with tiles on adjacent dies. This multi-functionality eliminates the need for separate switching fabric hardware dedicated solely to interdie communication, thereby reducing hardware duplication while maintaining full communication capability.
Solution Approach 2:
The patent merges the intradie and interdie communication functions into a single switching fabric structure on each die. By combining these functions, the system avoids duplicating switching fabric hardware and reduces overall device complexity while preserving the ability to handle both types of communication efficiently.
3Productivity
If the number of tiles per die is increased beyond manufacturing limits, then the parallelism is improved, but the manufacturing feasibility deteriorates
Solution Approach 1:
The patent segments the parallel processing workload across multiple manufacturable dies rather than attempting to fit all tiles on a single oversized die. Each die contains a feasible number of tiles that can be manufactured with current fabrication processes, while the stacked arrangement achieves the target total parallelism across the multi-die system.
Solution Approach 2:
The patent moves from a single-die two-dimensional layout to a multi-die three-dimensional stacked architecture. This dimensional transition allows the system to achieve high parallelism by stacking multiple feasibly-manufacturable dies vertically, bypassing the single-die manufacturing constraints while maintaining scalability.
Data Source
AI summary
Two or more die are stacked together in a stacked integrated circuit device. Each of the processors on these die is able to communicate with other processors on its die by sending data over the switching fabric of its respective die. The mechanism for sending data between processors on the same die (i.e. intradie communication) is reused for sending data between processors on different die (i.e. interdie communication). The reuse of the mechanism is enabled by assigning each processor a vertical neighbour on its opposing die. Each processor has an interdie connection that connects it to the output exchange bus of its neighbour. A processor is able to borrow the output exchange bus of its neighbour by sending data along the output exchange bus of its neighbour.