Semiconductor Package Assembly With Stacked Die Interface Routing
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Solution Overview
Problem
Existing semiconductor package assemblies face challenges in fulfilling channel requirements for integrating different components, lacking flexibility in channel design which affects electrical performance.
Innovation Solution
A semiconductor package assembly design featuring a bottom package with two semiconductor dies of different critical dimensions, where one die with a narrower dimension controls the top package and includes external interfaces for data transmission, and the other die with a wider dimension has internal interfaces, arranged to reduce routing path lengths and improve signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional semiconductor package assemblies are used, then manufacturing is straightforward, but channel design flexibility is insufficient
Solution Approach 1:
The package assembly is divided into multiple semiconductor dies (first die, second die, third die) with distinct functions. The first die contains control logic, the second die contains memory, and the third die provides additional functionality. This segmentation allows each die to be optimized independently for its specific function while providing flexibility in channel design between them.
Solution Approach 2:
The patent transitions from traditional lateral routing to vertical stacking, adding the vertical dimension to the package architecture. Multiple dies are stacked in the Z-direction with interconnections formed through via structures, enabling three-dimensional integration and significantly improving channel design flexibility while reducing lateral routing constraints.
2Reliability
If routing path lengths are reduced for better electrical performance, then signal propagation improves, but channel design becomes more constrained
Solution Approach 1:
By stacking dies vertically and forming interconnections through the substrate using via structures, the patent creates three-dimensional routing paths. This allows signal transmission in the vertical dimension, significantly reducing lateral routing path lengths and improving electrical performance while maintaining design flexibility through multiple vertical connection points.
Solution Approach 2:
The patent introduces intermediate connection structures (via structures, redistribution layers) that mediate between different dies. These intermediaries provide multiple connection points and routing options, allowing flexible channel design while maintaining short effective signal paths through optimized vertical interconnections.
3Adaptability or versatility
If multiple interfaces are added to a single die for better integration, then channel flexibility improves, but die size and complexity increase
Solution Approach 1:
Instead of adding multiple interfaces to a single die, the patent segments the functionality across multiple dies. Each die has a focused set of interfaces optimized for its specific function, avoiding the need for any single die to accommodate all interfaces, thus controlling die area while providing overall system flexibility.
Solution Approach 2:
The patent moves interface integration from the lateral plane to the vertical dimension by stacking dies. Each die in the stack provides specific interfaces, and the vertical interconnections enable communication between all dies, achieving high interface integration without increasing the lateral area of any individual die.
Data Source
AI summary
A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor die, a second semiconductor die and third semiconductor die. The first semiconductor die and the second semiconductor die are arranged side-by-side. The first semiconductor die includes a first interface and a second interface. The first interface is arranged on a first edge of the first semiconductor die. The second interface is arranged on a second edge of the first semiconductor die that is close to the second semiconductor die and connected to the first edge. The third semiconductor die is stacked on the first semiconductor die and the second semiconductor die, wherein the third semiconductor die is electrically connected to the first semiconductor die by the first interface, and wherein the first semiconductor die is electrically connected to the second semiconductor die by the second interface.