Stacked Die Package With Electrical Interposer
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Solution Overview
Problem
Conventional semiconductor packaging designs for stacking larger chips on top of smaller chips are hindered by complex and costly bond wire connections with high parasitic values, which are not well-suited for applications where the smaller chip generates more heat.
Innovation Solution
A semiconductor chip assembly that includes an electrical interposer providing a direct, low-resistance electrical connection between the larger chip and external terminals, allowing the smaller chip to be mounted on top of the larger chip with the interposer underneath, enabling efficient heat dissipation and reducing packaging complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bond wire connections are used to connect stacked chips, then electrical connections can be established, but the parasitic values are high and the design complexity increases
Solution Approach 1:
The patent introduces an intermediate substrate that acts as a mediator between the stacked chips. This substrate provides a platform for direct electrical contact through conductive regions, eliminating the need for complex bond wire connections while reducing parasitic values. The intermediate substrate serves as a stable intermediary structure that simplifies the overall connection architecture.
2Ease of operation
If the smaller chip is stacked on top of the larger chip, then terminals of the larger chip are electrically accessible, but heat dissipation from the smaller chip is compromised
Solution Approach 1:
The patent utilizes the vertical dimension by introducing an intermediate substrate between the stacked chips. This allows the smaller chip to be positioned above the larger chip while maintaining thermal contact with the substrate's conductive regions. The intermediate substrate creates a new dimensional layer that simultaneously enables both electrical accessibility and thermal management pathways.
3Reliability
If intermediate redistribution layers are used in chip stacking, then electrical connections can be achieved, but cost and design complexity increase
Solution Approach 1:
The patent extracts and eliminates the need for intermediate redistribution layers by using a simplified intermediate substrate with direct conductive regions. Instead of adding complex redistribution functionality, the design removes this layer entirely, relying on the substrate's inherent conductive structures to provide necessary electrical connections, thereby reducing manufacturing cost and simplifying the design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a low-cost, low-resistance electrical connection that is well-suited for heat management, reducing the circuit board footprint and improving the efficiency of semiconductor packaging.
Implementation Method 1
an electrical interposer having a first conductive surface disposed at a first end, a second conductive surface disposed at a second end that is opposite from the first end, and a conductive connection between the first and second conductive surfaces
Data Source
AI summary
A semiconductor chip assembly includes first and second semiconductor dies that each include opposite facing upper and lower sides and an outer edge side, and an electrical interposer having opposite facing first and second conductive surfaces and a conductive connection between the conductive surfaces. The second semiconductor die is mounted on top of the first semiconductor die and the interposer such that the lower side of the second semiconductor die faces the first semiconductor die and the interposer, a first lateral section of the second semiconductor die at least partially covers the upper side of the first semiconductor die, and a second lateral section of the second semiconductor die extends past the outer edge side of the first semiconductor die. The first conductive surface is electrically connected to a first terminal that is disposed on a lower side of the second semiconductor die.