Stacked Die Test Circuits for Post-Bond Isolation Testing
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Solution Overview
Problem
In stacked semiconductor devices, the inability to separately test individual dies after bonding complicates troubleshooting and defect identification, and the lack of post-bonding wafer acceptance tests can lead to unidentified bonding defects, reducing manufacturing yield.
Innovation Solution
Incorporating a control circuit and a transistor in the first die of a stacked semiconductor device, which allows for selective blocking of die-to-die interconnects, enabling independent testing of each die after bonding. Additionally, a bonding layer test line is included to test the bonding performance and electrical properties of the bonding layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bonding is performed to form stacked semiconductor devices, then device integration and three-dimensional circuit formation are achieved, but the ability to separately test individual dies after bonding is lost
Solution Approach 1:
The patent divides the stacked semiconductor device into separately controllable testing segments by introducing independent test circuits for each die. The control circuit can selectively activate test modes for individual dies (first die, second die) even after bonding, allowing separate testing without requiring physical separation of the bonded structure.
Solution Approach 2:
The patent introduces a control circuit as an intermediary component that mediates between the test signal input and the individual dies. This control circuit receives test signals and selectively routes them to specific dies through the bonded interconnects, enabling separate testing capability while maintaining the bonded structure.
2Ease of manufacture
If bonding is performed without post-bonding test capability, then manufacturing process is simplified, but bonding defects remain unidentified reducing yield
Solution Approach 1:
The patent implements preliminary testing capability built into the bonded structure itself. The test circuits and control mechanisms are integrated during the bonding process, enabling immediate post-bonding verification of bonding quality and electrical connections before the device proceeds to subsequent manufacturing steps.
Solution Approach 2:
The patent establishes a feedback mechanism where test signals are applied to the bonded structure and the responses are analyzed to determine bonding quality. This feedback loop allows real-time detection of bonding defects and provides information for process adjustment or defect correction.
3Measurement precision
If independent testing of each die is enabled after bonding, then defect identification improves, but device complexity increases
Solution Approach 1:
The patent implements multi-functional test circuits that can perform multiple testing operations through a unified structure. The same control circuit and test signal paths are used to test different dies in different modes, reducing the need for separate dedicated test structures for each die and thereby limiting the increase in complexity.
Data Source
AI summary
A control circuit is included in a first die of a stacked semiconductor device. The first die further includes a transistor that is electrically connected to the control circuit. The transistor is configured to be controlled by the control circuit to selectively block a die-to-die interconnect. In this way, the die-to-die interconnect may be selectively blocked to isolate the first die and a second die of the stacked semiconductor device for independent testing after bonding. This may increase the effectiveness of a testing to identify and isolate defects in the first die or the second die, which may further increase the effectiveness of performing rework or repair on the stacked semiconductor device.