3D Stacked Die Layout for Short-Path Intra-Stack Connections
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Solution Overview
Problem
The manufacturing process of 3D die-stacked semiconductor devices is complex and costly due to the need for multiple sets of high-cost lithographic masks and interference of through silicon vias with analog signals, complicating the design and arrangement of stacked dies.
Innovation Solution
A semiconductor structure with stacked dies featuring identical circuit layouts on each die, allowing for the use of a single set of masks and minimizing interference by aligning intra-stack connection circuits and using hybrid bonding to couple computation and memory circuits, while dummy circuits reduce interference from through silicon vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple sets of lithographic masks are used to produce dies with different pad arrangements, then routing and connection between different dies can be simplified, but manufacturing cost and complexity increase
Solution Approach 1:
The patent applies asymmetry by intentionally designing different pad arrangements on the first die versus the second die. The first die has pads arranged in a first pattern while the second die has pads arranged in a second pattern, allowing optimized routing connections between dies without requiring multiple mask sets for symmetric variations
Solution Approach 2:
Instead of using multiple masks to create different pad arrangements on identical dies, the patent inverts the approach by using a single mask set to produce dies with deliberately different pad patterns. This reversal simplifies the manufacturing process while achieving the same routing simplification goal
2Device complexity
If through silicon vias (TSVs) are adopted in 3D die-stacking technology, then vertical connection between dies is enabled, but interference with analog signal circuits occurs
Solution Approach 1:
The patent applies local quality by creating spatial separation between TSVs and analog signal circuits. The layout strategically positions TSVs in regions away from sensitive analog circuits, giving different parts of the die different functional qualities - high-density vertical interconnection in logic regions and low-interference zones in analog regions
Solution Approach 2:
The patent introduces redistribution layers (RDLs) as intermediary structures between TSVs and analog signal circuits. These RDLs act as mediators that route signals away from TSV interference zones, allowing vertical connections to be maintained while protecting sensitive analog circuits from harmful electromagnetic interference
3Adaptability or versatility
If dies with same functionalities are produced in different versions, then routing arrangement flexibility is improved, but manufacturing cost increases due to multiple mask sets
Solution Approach 1:
The patent applies universality by designing a single mask set that can produce multiple die versions with different pad arrangements through selective placement and orientation. The same mask pattern serves multiple functions by being used to create both first dies with a first pad arrangement and second dies with a second pad arrangement, eliminating the need for separate mask sets for each version
Data Source
AI summary
The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.