Stacked-Die Memory Controller With TSV Protocol Conversion
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Solution Overview
Problem
High-speed communication in semiconductor devices like HBM leads to increased latency and power consumption due to signal transmission through an external interposer.
Innovation Solution
A memory controller is integrated with vertically stacked core dies via through-silicon vias (TSVs), utilizing a protocol converter to align and convert signals for multi-phase communication, reducing the need for high-speed communication and eliminating the buffer die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed communication is performed through an external interposer, then communication speed is improved, but latency increases and power consumption increases
Solution Approach 1:
The patent merges the memory controller and core dies into a single integrated package, eliminating the external interposer. The logic die containing the memory controller is directly coupled with core dies through TSVs, creating a unified structure that reduces signal path length and eliminates intermediate communication interfaces, thereby reducing latency while maintaining high-speed communication capability
2Speed
If high-speed communication is performed through an external interposer, then communication speed is improved, but power consumption increases
Solution Approach 1:
By integrating the memory controller and core dies in a single package with direct TSV coupling, the patent eliminates the energy-consuming external interposer interface. The reduced signal transmission distance and removal of intermediate buffering operations significantly lower power consumption while preserving high-speed communication performance
3Reliability
If a buffer die is used for communication between logic die and core dies, then signal transmission is enabled, but device complexity increases
Solution Approach 1:
The patent extracts and removes the buffer die from the HBM structure, enabling direct communication between the logic die and core dies through TSVs. This elimination of the intermediate buffer layer simplifies the overall device structure, reduces the number of components, and lowers manufacturing complexity while maintaining reliable signal transmission through the direct TSV interface
Data Source
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AI summary
A semiconductor device includes at least one core die and a logic die communicating with the core die via a plurality of through-silicon vias. The logic die includes a memory controller configured to control a memory operation of the core die and a PHY region configured to receive first input signals based on a first protocol from the memory controller and transmit first output signals generated based on the first input signals to the core die via the plurality of TSVs. The PHY region includes a protocol converter configured to perform alignment processing on bits of the first input signals so as to convert the protocol of the first input signals into a second protocol and then output the first input signals based on the second protocol, wherein the second protocol supports multi-phase communication between the PHY region and the core die.