Stacked Die Fabrication with Hybrid Bonding Across Mixed Foundry Nodes
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Solution Overview
Problem
Conventional microelectronic packaging technologies face inefficiencies in integrating dies from different foundry nodes, wafer sizes, and form factors into 3DICs, leading to low yield and high costs due to the need for separate fabrication and packaging processes, and limitations in interconnect density and space utilization.
Innovation Solution
The use of die-to-wafer (D2W) or chip-to-wafer (C2W) techniques for direct hybrid bonding of variegated dies with different physical sizes and foundry nodes, allowing for high-density signal connections and efficient stacking within a wafer level packaging flow, using molding materials to fill lateral spaces and planarize surfaces for further bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate fabrication and packaging processes are used for integrating dies from different foundry nodes, then flexibility in die selection is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges separate fabrication and packaging processes into an integrated wafer-level process. Dies from different foundry nodes are fabricated on the same wafer using compatible process nodes, eliminating the need for separate packaging operations. The redistribution layer is formed directly on the wafer before dicing, combining multiple discrete steps into a unified manufacturing flow that reduces complexity while maintaining flexibility.
2Ease of manufacture
If conventional packaging techniques are used, then process simplicity is maintained, but interconnect density and space utilization deteriorate
Solution Approach 1:
The patent transitions from planar 2D packaging to 3D stacked architecture. Multiple layers of dies are vertically stacked with redistribution layers formed between them, enabling high-density interconnects in the vertical dimension. This three-dimensional arrangement dramatically improves space utilization and interconnect density while maintaining process simplicity through wafer-level integration.
3Adaptability or versatility
If dies of different sizes are integrated using conventional methods, then design flexibility is improved, but manufacturing precision and alignment deteriorate
Solution Approach 1:
The patent employs a universal wafer-level process that accommodates dies of different sizes, shapes, and foundry nodes on a single wafer. The redistribution layer is formed using standard photolithography and etching processes that can pattern interconnects for varied die geometries. Alignment marks and registration features ensure precise positioning of heterogeneous dies during wafer-level integration, maintaining manufacturing precision while enabling design flexibility.
Data Source
AI summary
Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.