Programmable Multiplexer Testing for Stacked Die I/O Mismatches
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Solution Overview
Problem
Existing methods for testing inter-die connections in stacked die applications fail to verify complete continuity when there is a mismatch between the number of input and output connections between the base die and the stacked die, leaving some interconnects unverified.
Innovation Solution
Implementing redundant through-die vias (TDVs) using flexible or standard design rules to create additional signal paths that can balance interconnection mismatches, and utilizing programmable multiplexers to form loop-back paths or employing built-in-test circuits to verify continuity across all connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan chain testing is used to verify interconnections between base die and stacked die, then continuity of matched I/O connections is verified, but connections with mismatched I/O pad counts cannot be fully tested
Solution Approach 1:
The patent introduces an intermediary testing mechanism that uses the programmable multiplexer to create virtual I/O pad correspondences. The multiplexer acts as a mediator that can dynamically map any I/O pad to any other I/O pad, enabling scan chain testing to work even when the base die and stacked die have mismatched I/O pad counts. This intermediary mechanism allows the test signal to be routed through the multiplexer to establish continuity paths that would otherwise not exist due to the mismatch.
Solution Approach 2:
The patent employs dynamic reconfiguration of the I/O connection mapping through the programmable multiplexer. Instead of a fixed one-to-one correspondence between I/O pads, the multiplexer allows dynamic assignment of I/O pad connections based on the specific testing requirements. This dynamic capability enables the system to adapt the I/O mapping to accommodate mismatched connection counts while still performing comprehensive continuity verification using scan chain testing.
2Reliability
If redundant through-die vias are implemented to balance interconnection mismatches, then complete conductivity verification is enabled, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent makes the through-die vias universal by implementing them with flexible or standard design rules that allow the same via structure to serve multiple functions. The redundant vias are not dedicated solely to testing but can be used for both normal operational interconnections and continuity verification. This multi-functionality reduces the need for separate test-specific structures and minimizes the overall device complexity while still enabling complete conductivity verification.
Solution Approach 2:
The patent changes the design parameters of the through-die vias by implementing them with flexible or standard design rules rather than fixed strict parameters. This parameter change allows the vias to be more easily integrated into the existing device architecture and reduces manufacturing complexity. The vias can tolerate a range of dimensional variations while still functioning correctly for both operational and testing purposes.
3Ease of manufacture
If flexible or standard design rules are used for redundant TDVs, then manufacturing yield is improved, but testing and detection difficulty increases
Solution Approach 1:
The patent implements a feedback mechanism through the scan chain testing system that provides continuous information about the continuity status of the through-die vias. The test signals are propagated through the vias and the results are fed back to indicate whether each via is conductive or defective. This feedback mechanism enables the detection and measurement of TDV continuity even when flexible or standard design rules are used, by systematically testing each via path and providing clear pass/fail indications.
Data Source
AI summary
A method and apparatus to test the inter-die interface between two or more semiconductor die in die stacking applications, where a mismatch exists between the number of input and output pads on a base die and the number of input and output pads on a stacked die. In a first embodiment, a number of through-die vias (TDVs) may be used to implement inter-die signal paths using standard or flexible design rules to maintain statistical TDV yield despite the lack of continuity verification of the inter-die signals paths. In alternate embodiments, programmable multiplexers may be utilized to share one or more inter-die connections between the base die and the one or more stacked die so as to facilitate testing and normal operation of each inter-die connection. In other embodiments, spare TDVs are utilized only during test operations, so as to accommodate the mismatch. In yet other embodiments, built-in-test (BIT) circuits are configured to perform logic operations using a plurality of inter-die input/output (I/O) signals to eliminate the need to implement an identical number of input and output ports between the base die and the one or more stacked die to facilitate inter-die testing.