Stacked Die Communication Network for Fine-Pitch Interconnects
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Solution Overview
Problem
Conventional microelectronic assemblies face challenges in reliably communicating large numbers of signals between multiple integrated circuit (IC) dies due to their small size, thermal constraints, and power delivery limitations, which restrict design flexibility and efficiency.
Innovation Solution
The microelectronic assemblies incorporate a package substrate with interconnects that allow direct coupling between dies, enabling a communication network within the substrate, which facilitates improved power delivery and signal speed while reducing package size, and include a combination of different pitch interconnects to accommodate various die configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional substrates are used to couple IC dies, then mechanical stability is achieved, but interconnect pitch is constrained by manufacturing, materials, and thermal considerations
Solution Approach 1:
The patent transitions from planar substrate-based interconnection to three-dimensional direct die-to-die bonding, enabling vertical stacking architectures. This dimensional change allows interconnects to pass through multiple die layers via through-die vias, achieving higher density interconnection without being constrained by conventional substrate manufacturing limits.
Solution Approach 2:
The patent introduces through-die vias and redistribution layers as intermediary structures that enable signal routing between stacked dies. These intermediaries facilitate direct communication between dies without requiring conventional substrate interconnection, thereby achieving finer interconnect pitch while maintaining manufacturing feasibility.
2Productivity
If multiple IC dies are stacked to improve integration density, then bandwidth and power efficiency improve, but thermal management and alignment precision become more challenging
Solution Approach 1:
The patent employs vertical stacking of multiple dies in the third dimension, allowing high integration density without increasing planar footprint. Through-die vias enable direct vertical interconnection, reducing signal path length and improving bandwidth while maintaining power efficiency through shorter interconnect paths.
Solution Approach 2:
The patent implements a nested architecture where multiple functional dies are stacked and interconnected vertically, with each die containing embedded vias and conductive structures. This nested arrangement allows compact integration of multiple processing elements, memory, and I/O functions in a vertically organized manner.
3Speed
If direct die-to-die coupling is implemented, then signal speed and power delivery improve, but manufacturing complexity and alignment requirements increase
Solution Approach 1:
The patent incorporates alignment features, guide structures, and pre-formed interconnect patterns on each die before stacking. Through-die vias are pre-positioned and pre-connected during die fabrication, enabling precise alignment during the stacking process without requiring complex real-time alignment systems.
Solution Approach 2:
The patent employs self-aligning bonding mechanisms where complementary features on adjacent dies automatically position themselves during bonding. The interconnect structures are designed to self-register, reducing the need for external alignment equipment and simplifying the manufacturing process while maintaining high precision.
Data Source
AI summary
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.