Wafer-Level Stacked Die Structure With Offset Interconnect Layout
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Solution Overview
Problem
Conventional semiconductor die stacks using gold wire loops are limited in height and configuration, leading to unreliable electrical connections and increased manufacturing complexity, especially when stacking more than two dies, and they restrict the miniaturization of semiconductor packages.
Innovation Solution
The use of conductive interconnects, such as copper pillars or pins, that extend from the active side of each die and are connected to a redistribution layer, allowing for closer package spacing and higher die density in stacked configurations without the need for additional substrates, enabling the stacking of multiple dies with varied orientations and sizes to accommodate the interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gold wire loops are used to electrically couple semiconductor dies, then electrical connections can be established, but the height of the die stack is limited and manufacturing complexity increases
Solution Approach 1:
The patent extracts the wire loop interconnect from the conventional die stack configuration and replaces it with conductive posts integrated into the substrate. This removal of the wire loop element simplifies the manufacturing process by eliminating the complex wire bonding steps while maintaining reliable electrical connections between dies.
Solution Approach 2:
The patent introduces conductive posts as an intermediary element between the substrate and the semiconductor dies. These posts serve as fixed interconnection points that simplify the bonding process by providing predetermined electrical connection points, thereby reducing manufacturing complexity while ensuring reliable electrical coupling.
2Quantity of substance
If multiple semiconductor dies are stacked vertically to increase capacity, then device capacity increases, but package size reduction is restricted
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked packaging by vertically arranging multiple semiconductor dies. This dimensional change allows capacity to increase by stacking dies in the vertical direction while the conductive posts enable compact integration that minimizes the horizontal footprint, thus controlling overall package size.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor dies are stacked vertically within a compact package footprint. The conductive posts are integrated within the substrate structure, allowing the dies to be nested in layers with optimized spacing, thereby increasing capacity without proportionally increasing package volume.
3Productivity
If conventional wire loop methods are used for stacking more than two dies, then electrical connections can be made, but connection reliability decreases and manufacturing becomes more complex
Solution Approach 1:
The patent performs preliminary action by pre-forming conductive posts on the substrate before die attachment. These posts are prepared in advance with precise positioning and electrical connectivity, which simplifies the subsequent die stacking process and ensures reliable electrical connections from the first die to multiple stacked dies without the complexity of wire looping through multiple layers.
Data Source
AI summary
A stacked die structure for a semiconductor device generally includes a primary level with a first die formed in a wafer, and a second level with a second die coupled to the first die. A third level includes a third die coupled to the second die. The levels have conductive first, second, and third interconnects, respectively, extending from active sides of the dies and may be bonded prior to stacking the dies. The dies may be stacked in an offset or rotated position relative to each other such that the interconnects extend beyond each of the other dies to contact a redistribution layer that forms electrical connections with external components. In some configurations, a fourth level having a fourth die and a conductive fourth interconnect is coupled to the third die and positioned laterally offset from the third die such that the third interconnect extends beyond the fourth die.