Stacked Die Package Using Wire Bonding and Direct Chip Attachment
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Solution Overview
Problem
The use of through-silicon vias (TSVs) in stacked semiconductor packages increases costs and decreases array efficiency, making it incompatible with cost-effective processes and reducing the usable memory array size.
Innovation Solution
A stacked die package is formed using direct chip attachment (DCA) for the master die and wire bonding for slave dies, eliminating the need for TSVs and incorporating inline redistribution layers (iRDLs) to facilitate signal transmission between dies via a substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used to couple semiconductor dice in a stacked package, then the dice can be vertically interconnected, but the manufacturing cost increases and array efficiency decreases
Solution Approach 1:
The patent extracts and eliminates the TSV process from the stacked die package manufacturing. Instead of forming through-silicon vias in each die, the invention uses wire bonding to connect dies to the substrate, removing the costly and complex TSV fabrication steps while maintaining vertical interconnection functionality through alternative means.
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support, electrical interconnection between dies via wire bonds, and signal routing. This multi-functional substrate approach replaces the specialized TSV interconnection function, eliminating the need for separate TSV formation processes in each die.
2Reliability
If through-silicon vias (TSVs) are used to form stacked semiconductor packages, then vertical interconnection is achieved, but the array efficiency (percentage of memory array size on active surface) decreases
Solution Approach 1:
The invention removes TSV structures from the die architecture, eliminating the space-consuming via holes and associated process steps. This extraction of the TSV requirement allows the entire active surface of each die to be dedicated to memory array fabrication, maximizing array efficiency.
3Reliability
If direct chip attachment (DCA) features are used to couple a first die to a substrate, then connection reliability is improved, but the process complexity increases compared to traditional methods
Solution Approach 1:
The patent merges the DCA feature formation with the substrate fabrication process. The DCA features are formed as integral parts of the substrate during its manufacturing, eliminating the need for separate attachment process steps. This integration maintains high connection reliability while reducing overall process complexity.
Data Source
AI summary
Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.