Stacked Memory Die Parallel Access for Bandwidth and Die Area
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Solution Overview
Problem
The use of through-die vias in stacked semiconductor memory die configurations increases die size due to area consumption, necessitating efficient schemes for coupling stacked memory die.
Innovation Solution
Implementing a stacked configuration where a master memory die and a slave memory die perform parallel memory access operations, with the master die aggregating data from both, using through-die vias to transmit signals and data between the dies, thereby reducing die area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through-die vias are used to couple stacked memory die, then memory capacity is increased, but die area is consumed and die size increases
Solution Approach 1:
The patent transitions from planar memory expansion to vertical stacking by coupling multiple memory die through the third dimension (depth). Through-die vias enable interconnection between die stacked vertically, allowing memory capacity to increase without proportionally increasing die area. The master die coordinates parallel access operations across multiple slave die in the stack, achieving high-capacity storage while maintaining compact die footprint.
2Quantity of substance
If through-die vias are used to couple stacked memory die, then memory capacity is increased, but die size increases
Solution Approach 1:
The invention moves memory expansion from the two-dimensional plane to the three-dimensional vertical dimension. By stacking memory die and using through-die vias for interconnection, the system achieves increased memory capacity without increasing the lateral dimensions (length and width) of individual die. The master die manages parallel operations across vertically stacked slave die, enabling high capacity in a compact form factor.
3Productivity
If parallel memory access operations are performed across stacked die, then data aggregation efficiency is improved, but signal transmission complexity increases
Solution Approach 1:
The patent merges multiple memory access operations into unified parallel transactions coordinated by the master die. The master die aggregates data from multiple slave die simultaneously, combining multiple data streams into a coordinated output. This merging approach improves productivity by enabling parallel access across the stack while the master die's control logic manages the signal transmission complexity through centralized coordination.
Solution Approach 2:
The master die acts as an intermediary between the external interface and the stacked slave die. It receives commands, distributes them to appropriate slave die, aggregates their responses, and presents unified data output. This intermediary role simplifies the overall system by providing a single point of control that manages signal transmission complexity while enabling efficient parallel access operations across the memory stack.
Data Source
AI summary
A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.