Stacked Die Package Pillar Layout for Universal Redistribution Routing
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Solution Overview
Problem
The complexity of manufacturing semiconductor packages with stacked dies is increased due to the need for modifying the layout of the redistribution structure with different die configurations, leading to increased production costs and reduced productivity.
Innovation Solution
A manufacturing process where conductive pillars are formed on semiconductor devices with a specific layout that remains consistent across different device arrangements, allowing for a standardized redistribution structure formation, simplifying the process and reducing costs by maintaining the same pillar layout despite varying device configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the layout of the redistribution structure is modified to accommodate different die configurations, then the semiconductor package can adapt to various stacked die arrangements, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies universality by designing a standardized redistribution structure layout that can serve multiple different stacked die configurations. Instead of creating custom layouts for each configuration, a single universal layout is used that accommodates various die arrangements through flexible electrical connection designs, thereby reducing manufacturing process complexity while maintaining adaptability.
Solution Approach 2:
The redistribution structure is segmented into modular components that can be independently configured. This segmentation allows the same overall layout to adapt to different die configurations by reconfiguring individual segments rather than modifying the entire layout, thus maintaining manufacturing simplicity while achieving versatility.
2Reliability
If the layout of the redistribution structure is modified for each die configuration, then electrical connection requirements are met, but production costs increase
Solution Approach 1:
A universal redistribution structure layout is implemented that can reliably serve multiple die configurations without requiring custom modifications. This standardization reduces production costs by enabling bulk manufacturing of identical redistribution structures while maintaining electrical connection reliability through proven design patterns that work across different configurations.
Solution Approach 2:
The patent utilizes parameter changes in the electrical connection design, such as adjustable trace routing, variable pad configurations, and flexible via placements within the standardized layout. These parameter variations allow the same layout to meet different electrical connection requirements for various die configurations without increasing production costs.
3Reliability
If custom redistribution structure layouts are created for different die configurations, then specific electrical connection requirements are satisfied, but productivity decreases
Solution Approach 1:
The standardized redistribution structure layout enables a single manufacturing process to produce reliable electrical connections for multiple die configurations. This eliminates the need for separate manufacturing processes for each configuration, thereby increasing productivity while maintaining connection reliability through the proven universal design.
Solution Approach 2:
The universal redistribution structure layout is designed in advance to anticipate and accommodate various die configurations. This preliminary design action ensures that the same layout can be used for different configurations without requiring subsequent modifications, thus maintaining high manufacturing productivity while ensuring reliable electrical connections.
Data Source
AI summary
A semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed, wherein the plurality of conductive pillars disposed by the same side of the upper semiconductor device and the upper semiconductor device comprises a cantilever part cantilevered over the at least one lower semiconductor device. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over the upper semiconductor device and the encapsulating material.