Stacked Die Package RDL Flip-Chip Interconnect
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Solution Overview
Problem
Conventional stacked die semiconductor packages face challenges in reducing parasitic inductance and packaging costs due to the use of bond wires, which also limit power density and increase package area.
Innovation Solution
The implementation of a redistribution layer (RDL) on the bottom semiconductor die for flip-chip mounting of the top die, eliminating the need for bond wires and enabling die-to-die interconnections through flip-chip bumps, along with a leadframe design that includes a die pad and lead terminals, reduces parasitic inductance and packaging costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bond wires are used to interconnect stacked die, then electrical connections between die are established, but parasitic inductance increases and package area increases
Solution Approach 1:
The patent extracts and removes the bond wires from the stacked die interconnection system. Instead of using bond wires to connect the top die to the bottom die, the invention directly attaches the top die to the bottom die through die-to-die bonding, eliminating the intermediate bond wire elements that generate parasitic inductance.
Solution Approach 2:
The patent transitions from a three-dimensional wire-based interconnection approach to a direct surface-to-surface bonding approach. By changing the interconnection dimension from wire-like (1D) to planar contact (2D), the parasitic inductance is significantly reduced while maintaining electrical connectivity.
2Reliability
If bond wires are used for die interconnection, then electrical connectivity is achieved, but packaging cost increases
Solution Approach 1:
The invention removes bond wires from the packaging process, eliminating the material cost, handling complexity, and quality control requirements associated with bond wire attachment. This direct die bonding approach simplifies the manufacturing process and reduces overall packaging costs.
3Reliability
If bond wires are used for interconnection, then die can be connected, but package area increases
Solution Approach 1:
By removing bond wires and their associated routing space, the patent significantly reduces the lateral space required for die interconnection. The direct die-to-die bonding approach allows for more compact package layouts, reducing the overall package footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances power density, reduces packaging costs, and minimizes package size by eliminating bond wires, while maintaining effective die-to-die interconnections through flip-chip bumps and RDLs.
Implementation Method 1
a bottom die having a back side that is attached by a die attach material to the die pad
Data Source
AI summary
A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals.