Stacked Semiconductor Die Package with Redistribution Layer
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Solution Overview
Problem
Current semiconductor package structures, such as dual-dies fan-out WLCSP and 3D PoP, face challenges with size, warpage, and high fabrication costs due to increased complexity and area wastage, while TSV technology is costly and inefficient in reducing package thickness.
Innovation Solution
A semiconductor package structure is developed with vertically stacked semiconductor dies and a redistribution layer structure, surrounded by a molding compound, which allows for efficient integration of multiple dies without increasing the package size, using conductive vias and redistribution layers to connect the dies electrically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual-dies fan-out WLCSP structure is used to increase I/O pin count and IC density, then integration is improved, but package size becomes too big and warpage occurs
Solution Approach 1:
The patent transitions from a planar side-by-side dual-die arrangement to a vertical stacked configuration. The second die is positioned directly above the first die, utilizing the vertical dimension (Z-axis) to achieve higher integration density without increasing the package footprint. This dimensional change directly resolves the contradiction by maintaining I/O pin count while reducing package area.
2Adaptability or versatility
If TSV technology is used to penetrate multiple dies, then integration is improved, but fabrication cost increases and die area is wasted
Solution Approach 1:
The patent extracts and eliminates the TSV (Through-Silicon Via) process from the manufacturing workflow. Instead of forming penetrating vias through the silicon substrate, the invention uses alternative interconnection methods such as bump bonds or wire bonds that connect dies vertically without requiring costly TSV fabrication steps. This extraction of the TSV process directly reduces fabrication cost while maintaining multi-die integration capability.
3Adaptability or versatility
If 3D PoP structure stacks top package on bottom package, then integration is improved, but thickness cannot be reduced further
Solution Approach 1:
The patent merges the package substrate and die support functions into a single integrated structure. Rather than stacking separate packages (bottom package, intermediate substrate, top package), the invention integrates multiple dies directly onto a common substrate with shared interconnection resources. This merging eliminates redundant structural layers and reduces overall package thickness while maintaining integration benefits.
4Area of stationary object
If vertically stacked semiconductor dies are used, then package size is reduced, but electrical connection complexity increases
Solution Approach 1:
The patent implements a universal redistribution layer structure that serves multiple functions simultaneously: it provides electrical interconnection between stacked dies, performs signal routing, and enables I/O expansion. This multi-functional RDL design simplifies the overall electrical connection system by consolidating multiple specialized layers into a single versatile structure, reducing connection complexity despite the vertical stacking configuration.
Data Source
AI summary
A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor die including a first active surface and a first non-active surface. The semiconductor package structure also includes a second semiconductor die including a second active surface and a second non-active surface. The second semiconductor die is stacked on the first semiconductor die. The first non-active surface faces the second non-active surface. The semiconductor package structure further includes a first redistribution layer (RDL) structure. The first active surface faces the first RDL structure. In addition, the semiconductor package structure includes a second RDL structure. The second active surface faces the second RDL structure.