Stacked Die Seal Ring Structure for Delamination-Resistant Dicing
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in effectively bonding and dicing stacked dies to prevent delamination and moisture ingress while maintaining electrical connectivity and optical integrity, particularly in CMOS image sensors with complex interconnection structures.
Innovation Solution
The implementation of a semiconductor structure with alternating horizontal and vertical interconnection layers, seal ring structures, and redistribution layers, along with RDL seal rings, to guide stress vertically and isolate electrical paths, thereby reducing delamination and moisture ingress during dicing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level bonding and dicing process is used to fabricate stacked die, then productivity is improved, but delamination and moisture ingress occur during dicing
Solution Approach 1:
The patent applies preliminary action by forming stress guiding features and RDL seal rings before the dicing process. These features are pre-configured in the wafer stack to guide stress vertically during subsequent dicing operations, preventing delamination and moisture ingress before they can occur. The stress guiding features are created during wafer fabrication, enabling the dicing process to proceed without causing harmful horizontal stress propagation.
2Ease of manufacture
If dicing process is conducted on wafer-level package, then stacked die are obtained, but moisture ingress and delamination occur
Solution Approach 1:
The patent introduces RDL seal rings as intermediary structures that act as barriers between the external environment and the internal circuit regions. These seal rings, formed in the redistribution layer, create a protective boundary that prevents moisture ingress during dicing and subsequent operation. The seal rings function as a mediator that allows the dicing process to proceed while blocking the harmful pathway for moisture entry.
3Reliability
If complex interconnection structures are used in CMOS image sensors, then optical integrity is improved, but stress propagation during dicing causes delamination
Solution Approach 1:
The patent applies dimensionality change by introducing vertical stress guidance through alternating horizontal and vertical interconnection layers. Instead of allowing stress to propagate horizontally along the bonding interface (which causes delamination), the structured interconnection layers redirect stress vertically through the wafer thickness. This dimensional redirection of stress paths preserves bonding interface strength while maintaining the complex interconnection structures needed for optical integrity.
Data Source
AI summary
A semiconductor structure includes a first die and a second die. The first die includes a first semiconductor substrate, a first integrated circuit disposed on the first semiconductor substrate, and a first metal seal ring structure disposed on the first semiconductor substrate and surrounding the first integrated circuit. The second die includes a second semiconductor substrate, a second integrated circuit disposed on the second semiconductor substrate, and a second metal seal ring structure disposed on the second semiconductor substrate and surrounding the second integrated circuit. The second die is disposed over the first die, the second integrated circuit is electrically connected and bonded to the first integrated circuit, and the second metal seal ring structure is bonded to the first metal seal ring structure.