Stacked Semiconductor Die Sealing for Thermal Stress Cracking
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Solution Overview
Problem
Existing semiconductor devices and manufacturing methods face challenges in bonding processes, leading to delamination and crack formation due to thermal mismatch stresses, particularly in stacked semiconductor devices, which can render the structure non-functional.
Innovation Solution
A polysilazane-based dielectric material is used to form a sealing layer that seals non-bond areas between semiconductor dies and wafers, enhancing adhesion and reducing stress by converting to silicon oxide through thermal treatment, thereby improving bonding interface integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bonding processes are used to stack semiconductor devices, then device integration and size reduction are achieved, but thermal mismatch stresses cause delamination and crack formation
Solution Approach 1:
A sealing layer comprising a polysilazane-based dielectric material is introduced as an intermediary between the bonding interface and the external environment. This sealing layer fills non-bond areas and seals the bonding interface, preventing moisture and contaminants from penetrating while accommodating thermal expansion differences, thereby eliminating the direct stress pathway that caused delamination and cracking
Solution Approach 2:
The sealing layer is applied in advance to the bonding interface before final device operation. It serves as a pre-established protective barrier that cushions against thermal mismatch stresses and environmental degradation, preventing delamination and crack formation before they can occur during subsequent thermal cycling or operation
2Ease of manufacture
If conventional bonding methods are used, then manufacturing simplicity is maintained, but delamination and cracks occur due to thermal stress
Solution Approach 1:
The polysilazane-based sealing layer acts as a mediator between the bonded semiconductor structures. It is applied conformally to the bonding interface and cures to form a stress-absorbing barrier that protects against thermal mismatch stresses without complicating the overall manufacturing flow, as it can be deposited using standard PECVD equipment
Solution Approach 2:
The sealing layer material undergoes parameter changes through in-situ conversion from polysilazane to silicon oxide within the PECVD reactor. This transformation changes the material's physical and chemical properties, creating a stable, low-stress final structure that is resistant to thermal mismatch while maintaining manufacturing simplicity through a single integrated process step
3Device complexity
If non-bond areas are left exposed, then manufacturing complexity is reduced, but moisture and contaminants penetrate causing device failure
Solution Approach 1:
The sealing layer serves as an intermediary barrier that fills and seals non-bond areas at the bonding interface. It prevents moisture and contaminants from penetrating into the bonding interface while maintaining a relatively simple structure that does not significantly increase device complexity or require additional processing steps beyond the standard bonding sequence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The sealing layer effectively prevents delamination and crack formation, ensuring the structural integrity and functionality of stacked semiconductor devices by increasing bonding strength and reducing thermal stress.
Implementation Method 1
A polysilazane-based dielectric material is used to form a sealing layer that seals non-bond areas between semiconductor dies and wafers, enhancing adhesion and reducing stress by converting to silicon oxide through thermal treatment
Implementation Method 2
The sealing layer effectively prevents delamination and crack formation, ensuring the structural integrity and functionality of stacked semiconductor devices by increasing bonding strength and reducing thermal stress
Data Source
AI summary
A semiconductor device includes a first semiconductor die, a second semiconductor die bonded to the first semiconductor die, a sealing layer, and an encapsulant disposed on the first semiconductor die and laterally covering the sealing layer and the second semiconductor die. The second semiconductor die is bent with an edge of the second semiconductor die curving upwardly, where a non-bond area is at a periphery of a bonding interface of the first and second semiconductor dies. The sealing layer seals the non-bond area of the first and second semiconductor dies.