Stacked Die Package Thermal Management via Embedded Solder Bumps
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated circuit packages face challenges with increased thermal resistance and high manufacturing costs due to the use of organic adhesives and inorganic spacers in stacked die configurations, which hinder miniaturization and performance.
Innovation Solution
The solution involves forming bond pads on a wafer, depositing solder bumps, embedding them in a mold compound, and creating recesses to expose the bumps, allowing for stacked die configurations with improved thermal management and reduced thickness through planarization and singulation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If organic adhesive or inorganic spacers are used to achieve space between stacked dies for wire bonding, then the dies can be stacked with proper spacing, but thermal performance deteriorates due to inability to remove heat through these materials
Solution Approach 1:
The patent removes the thermal barrier materials (organic adhesive and inorganic spacers) from between the stacked dies, extracting the harmful element that blocked heat flow. This allows direct thermal contact between dies and the heat dissipation path, resolving the contradiction by eliminating the material that caused thermal deterioration while maintaining die stacking capability through alternative bonding methods
Solution Approach 2:
The patent introduces a new intermediary material with superior thermal conductivity properties to replace the traditional adhesive and spacer materials. This mediator enables both the mechanical spacing/bonding function and the thermal conduction function simultaneously, allowing heat to flow efficiently through the stacked die structure while maintaining proper die separation and electrical insulation
2Productivity
If the number of dies in the stack increases, then more integrated circuit functions are achieved, but thermal resistance increases at a faster rate
Solution Approach 1:
The patent transitions from horizontal heat dissipation pathways to vertical heat dissipation pathways by improving thermal conduction through the stacked die structure. By enhancing thermal contact in the vertical dimension and providing dedicated heat dissipation paths through the stack, the system can accommodate more dies without proportionally increasing thermal resistance, as heat can now flow efficiently in the vertical direction through the improved thermal interface materials
3Ease of operation
If conventional semiconductor package structures are used, then adequate space is provided for mounting, but the package size becomes considerably larger than the semiconductor chip
Solution Approach 1:
The patent merges the semiconductor chip with the package structure by eliminating separate package substrates and mounting layers. The chip is directly bonded to the package casing or heat dissipation structure, combining multiple functions (structural support, electrical connection, heat dissipation) into a single integrated structure. This merging reduces the overall package volume to be closer to the chip size while maintaining adequate mounting space through optimized vertical stacking
4Ease of manufacture
If conventional fabrication methods are used for semiconductor packages, then adequate manufacturing processes are provided, but the number of processes is relatively large leading to high costs
Solution Approach 1:
The patent employs universal materials and processes that serve multiple functions simultaneously. For example, the thermal interface material also provides electrical insulation and mechanical bonding; the package casing serves as both structural support and heat dissipation path. This multi-functionality reduces the number of separate manufacturing processes needed, as single steps accomplish multiple objectives that previously required separate dedicated processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces thermal resistance and manufacturing costs, enabling the creation of thinner, more integrated, and high-performance semiconductor packages with simplified processes.
Implementation Method 1
A solder bump is deposited on one or more bond pads
Implementation Method 2
The bond pads and the solder bump are embedded within a mold compound formed on the wafer
Data Source
AI summary
An integrated circuit package system is provided including providing a wafer with bond pads formed on the wafer. A solder bump is deposited on one or more bond pads. The bond pads and the solder bump are embedded within a mold compound formed on the wafer. A groove is formed in the mold compound to expose a portion of the solder bump. The wafer is singulated into individual die structures at the groove.