Stacked Die Support Structure for Wirebonding and Tilt Control
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Solution Overview
Problem
Vertically stacked semiconductor dies with different sizes or footprints face challenges in wirebonding and tilting issues due to uneven encapsulation of the controller die, complicating manufacturing and increasing costs.
Innovation Solution
The use of support members with a coefficient of thermal expansion matching the dies, formed from semiconductor materials like silicon, which are attached to the package substrate and allow for direct mounting of memory dies without initial encapsulation of the controller die, reducing thermal stresses and eliminating high-temperature molding steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked dies with different sizes are used to increase density, then die density is improved, but wirebonding difficulty increases and die tilting occurs
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary component between the controller die and memory dies. The interposer has a first surface that contacts the controller die and a second surface that contacts the memory dies, acting as a mediator to accommodate size mismatches and enable proper wirebonding connections despite the different footprints of stacked dies
2Quantity of substance
If vertically stacked dies with different sizes are used to increase density, then die density is improved, but die tilting occurs
Solution Approach 1:
The interposer substrate serves as a stable intermediary platform that provides a uniform mounting surface for the memory dies, preventing tilting by distributing mechanical stresses evenly across the die stack and accommodating footprint differences between controller and memory dies
3Reliability
If initial encapsulation of controller die is performed before stacking, then die protection is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies die-attach material to the interposer substrate in advance before mounting the memory dies, preparing the bonding surface beforehand to facilitate subsequent die stacking and wirebonding operations, thereby simplifying the overall manufacturing process
Solution Approach 2:
The manufacturing process is segmented into distinct stages: first forming wirebonds between package substrate and controller die, then separately forming wirebonds between interposer and memory dies, and finally bonding the interposer assembly to the controller die, allowing each sub-assembly to be prepared independently
4Reliability
If high-temperature molding steps are used for encapsulation, then die protection is improved, but thermal stresses increase
Solution Approach 1:
The patent changes the bonding parameters by using die-attach material bonding at controlled temperatures instead of high-temperature molding, and employs wirebonding techniques that operate at lower temperatures, thereby reducing thermal stresses on the stacked dies while still achieving reliable connections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies manufacturing, reduces thermal stresses, prevents die tilting, and facilitates easier wirebonding by maintaining a uniform die-attach material thickness and eliminating the need for complex cavity formation in the package substrate.
Implementation Method 1
support members with a coefficient of thermal expansion matching the dies, formed from semiconductor materials like silicon
Data Source
AI summary
Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.