Stacked Die Test Circuits for Post-Bond Isolation and Defect Diagnosis

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Solution Overview

Problem

In the semiconductor industry, stacked semiconductor devices pose challenges in troubleshooting and defect identification due to the lack of separate testing of individual dies after bonding, which can lead to unidentified bonding defects and reduced manufacturing yield.

Innovation Solution

Incorporating a control circuit with a transistor in one die to selectively block die-to-die interconnects, allowing for independent testing of each die, and including a bonding layer test line to evaluate the bonding performance between dies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If separate testing of individual dies is implemented after bonding, then defect identification capability is improved, but device complexity increases due to additional control circuits and test infrastructure requirements

Engineering Contradiction:
Improvedefect identification capabilityVSAvoidtesting system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the stacked semiconductor device into individually testable segments by implementing control circuits that can selectively isolate each die. The control circuit includes a first switch element connected in parallel with a first through-substrate via, allowing independent electrical isolation of each die for separate testing while maintaining the stacked structure integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces control circuits and switch elements as intermediary components between the dies and test equipment. These control circuits act as mediators that enable selective electrical connection or isolation of individual dies during testing, facilitating defect identification without requiring complete disassembly of the stacked device.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If bonding defects remain unidentified, then manufacturing yield decreases, but implementing comprehensive testing increases manufacturing process complexity

Engineering Contradiction:
Improvemanufacturing yieldVSAvoidtesting process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements testing capabilities that can be exercised after bonding to identify defects early in the manufacturing process. The control circuits are designed to enable post-bonding verification of inter-die connections, allowing defects to be detected and addressed before final product completion, thereby improving yield without requiring overly complex final inspection processes.

Inventive Principle:
Principle #10Preliminary action

3Difficulty of detecting and measuring

If independent die testing is enabled, then troubleshooting effectiveness is improved, but the time required for testing increases due to sequential isolation and testing of each die

Engineering Contradiction:
Improvetroubleshooting effectivenessVSAvoidtesting time
Core Design Contradiction:
Difficulty of detecting and measuringVSLoss of time

Solution Approach 1:

The patent implements dynamic control of electrical connections through switch elements that can rapidly transition between connected and isolated states. The control circuit is designed to sequentially activate or deactivate switch elements, enabling fast isolation and testing of individual dies without manual reconfiguration, thereby reducing overall testing time while maintaining effective troubleshooting capability.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11935798B2Stacked semiconductor device test circuits and methods of use
Publication Date: 2024.03.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11935798B2 patent drawing
  • US11935798B2 patent drawing
  • US11935798B2 patent drawing

AI summary

A control circuit is included in a first die of a stacked semiconductor device. The first die further includes a transistor that is electrically connected to the control circuit. The transistor is configured to be controlled by the control circuit to selectively block a die-to-die interconnect. In this way, the die-to-die interconnect may be selectively blocked to isolate the first die and a second die of the stacked semiconductor device for independent testing after bonding. This may increase the effectiveness of a testing to identify and isolate defects in the first die or the second die, which may further increase the effectiveness of performing rework or repair on the stacked semiconductor device.