Stacked Semiconductor Die Assembly With Peripheral Thermal Transfer Path

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Solution Overview

Problem

Vertically-stacked semiconductor die packages face challenges in heat dissipation, leading to increased operating temperatures due to additive heat from individual dies, which limits the maximum operating temperature of the device, especially as die density increases and when different types of dies are stacked.

Innovation Solution

The implementation of a thermal transfer structure (TTS) with a highly conductive material, such as copper or aluminum, that includes a dam member attached to the peripheral region of the first die and a cover over the stack of second dies, along with an underfill material and thermally conductive elements, to create efficient heat dissipation paths and maintain operating temperatures below the maximum limit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If multiple semiconductor dies are vertically stacked to increase processing power without increasing package footprint, then the functional capacity of the package is improved, but the heat dissipation capability deteriorates due to additive heat from individual dies

Engineering Contradiction:
Improveprocessing powerVSAvoidoperating temperature
Core Design Contradiction:
PowerVSTemperature

Solution Approach 1:

The patent transitions from planar heat dissipation to three-dimensional thermal management by stacking dies vertically and implementing thermal paths that conduct heat in the vertical dimension through TSVs and thermal interface materials, allowing heat to be dissipated through multiple spatial dimensions rather than being confined to a single plane

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces thermal interface materials as intermediary substances between stacked dies and heat dissipation structures. These materials facilitate efficient thermal coupling and heat transfer, acting as mediators that bridge the thermal gap between solid die surfaces and heat dissipation pathways

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If die density is increased to meet operating parameters, then the functional capacity is improved, but the heat dissipation capability deteriorates due to reduced space for thermal management

Engineering Contradiction:
Improvefunctional capacityVSAvoidoperating temperature
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent segments the thermal management system into multiple independent pathways, with each die having its own thermal coupling structures and heat dissipation routes. This segmentation allows heat from each die to be managed separately, preventing heat accumulation even as die density increases

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent utilizes vertical stacking and three-dimensional thermal pathways to accommodate higher die density. By moving from two-dimensional package layouts to three-dimensional stacked architectures with vertical thermal conduction paths, the system can pack more dies without compromising thermal management capability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If different types of dies are stacked in the die stack, then the functional versatility is improved, but the maximum operating temperature is limited to the die with the lowest maximum operating temperature

Engineering Contradiction:
Improvefunctional versatilityVSAvoidmaximum operating temperature
Core Design Contradiction:
Adaptability or versatilityVSTemperature

Solution Approach 1:

The patent applies local quality by providing customized thermal management solutions for each die type in the stack. Different thermal interface materials, thermal conductivities, and heat dissipation structures can be tailored to match the specific thermal characteristics and operating temperature requirements of each die type, allowing heterogeneous stacking without being constrained by the lowest temperature tolerance die

Inventive Principle:
Principle #3Local quality

4Reliability

If through-silicon vias (TSVs) are used to electrically couple bond pads of individual dies with adjacent dies, then the electrical connectivity is improved, but the thermal management capability deteriorates due to additional heat generation from interconnections

Engineering Contradiction:
Improveelectrical connectivityVSAvoidoperating temperature
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent makes TSVs multi-functional by designing them to serve both electrical interconnection and thermal conduction purposes. The same vertical vias that provide electrical coupling between dies are configured with thermally conductive materials to simultaneously establish heat dissipation pathways, eliminating the need for separate thermal management structures and reducing overall heat accumulation

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively lowers the operating temperatures of individual dies, preventing them from exceeding their maximum temperatures and enhancing thermal dissipation, even in hybrid memory cube configurations where logic dies operate at higher power levels than memory dies.

Implementation Method 1

The implementation of a thermal transfer structure (TTS) with a highly conductive material, such as copper or aluminum... to create efficient heat dissipation paths

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20230395463A1Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
Publication Date: 2023.12.07 MICRON TECHNOLOGY INC
  • US20230395463A1 patent drawing
  • US20230395463A1 patent drawing
  • US20230395463A1 patent drawing

AI summary

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.