Stacked Die IC Package with Trace Frame Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge lies in developing an integrated circuit package stacking system that can accommodate increasing memory capacity within standard package formats, while avoiding costly redesigns and delays, as existing technologies struggle to efficiently package multiple chip types, such as processors and memory, in a single enclosure without compromising performance or increasing costs.
Innovation Solution
The proposed solution involves a trace frame system with encapsulant, bonding pads along its length and width, and conductive traces connecting them in a one-to-one correspondence, allowing for flexible packaging of integrated circuits in either rectangular or square formats without design changes, enabling the stacking of multiple chips in a single package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple integrated circuits are packaged together in a single enclosure to increase capacity, then device capacity is increased, but packaging complexity and difficulty increase
Solution Approach 1:
The patent implements stacking multiple integrated circuit dies vertically one on top of another within a single package enclosure, similar to nested dolls. This vertical stacking approach allows multiple devices to be contained within the same footprint, increasing capacity without proportionally increasing packaging complexity.
Solution Approach 2:
The patent transitions from horizontal placement of integrated circuits to vertical stacking, utilizing the third dimension (height) for packaging. This dimensional change allows multiple devices to coexist in the same package outline without increasing lateral dimensions, thereby increasing capacity while managing packaging complexity.
2Adaptability or versatility
If devices are redesigned to support different interface geometries to maintain standard formats, then adaptability is improved, but development cost and time increase
Solution Approach 1:
The patent creates a universal package design with standardized bonding pad arrangements that can interface with multiple standard formats (Secure Digital and Compact Flash). The same integrated circuit device can be packaged in this universal format without redesign, enabling it to support both SD and CF interfaces, thereby improving adaptability while avoiding development delays.
3Quantity of substance
If more integrated circuits are packed into standard package formats to increase capacity, then device capacity is increased, but manufacturing difficulty increases
Solution Approach 1:
The patent divides the package into discrete stacked dies, each with its own bonding pads and interconnections. This segmentation allows for modular manufacturing where each die can be prepared and tested independently before stacking, simplifying the overall manufacturing process while achieving high capacity within standard formats.
Data Source
AI summary
An integrated circuit package system includes a trace frame includes: an encapsulant; a first series of bonding pads along a length of the encapsulant; a second series of the bonding pads along a width of the encapsulant; conductive traces for connecting the bonding pads of the first series to the bonding pads of the second series in a one to one correspondence; and a first integrated circuit die on the encapsulant and on the conductive traces that extend beyond the first integrated circuit die.