3D Stacked Die Interconnect Layout for Reusable TSV Interfaces
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Solution Overview
Problem
Existing three-dimensional integrated circuits (3D ICs) face challenges in efficiently routing traffic through vertically stacked semiconductor dies due to misalignment of interconnects between different types of dies and the need for multiple masks, which increases costs and restricts placement of active devices.
Innovation Solution
The implementation of a system that uses non-full-through silicon vias (TSVs) and additional bonding pad interfaces with metal layers to route signals vertically and horizontally between dies, allowing for flexible interconnect configurations without requiring TSVs to traverse entirely through each die, thus enabling alignment of power and signal connections between different functionality dies using a single mask.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple masks are used to fabricate different interfaces for different dies, then adaptability to different applications is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements a universal interface design where a single mask pattern on the first die can serve multiple different second dies through selective bonding. The first die contains a plurality of interfaces that can be selectively bonded to different second dies, allowing the same first die to be used in various 3D IC configurations without requiring custom masks for each application.
2Manufacturing precision
If TSVs are aligned between stacked dies of the same type, then manufacturing precision is improved, but adaptability to different die types deteriorates
Solution Approach 1:
The patent segments the interconnect structure into two parts: TSVs that traverse through the first die and bonding pad interfaces at the top surface. This segmentation allows the TSV locations to be fixed during fabrication (maintaining manufacturing precision) while the bonding pad interfaces can be selectively bonded to different second dies (enabling adaptability to different die types).
Solution Approach 2:
The patent moves the adaptability from the vertical alignment dimension to the horizontal bonding dimension. Instead of aligning TSVs vertically between different die types, the first die provides multiple bonding pad interfaces at its top surface that can be selectively bonded to different second dies, transferring the interconnect function to a different spatial dimension.
3Reliability
If memory array banks are kept intact without perforation, then reliability of memory function is improved, but device complexity increases due to restricted interconnect locations
Solution Approach 1:
The patent resolves the location restriction by moving interconnect interfaces to the top surface of the first die in a different vertical dimension. Memory array banks remain intact on the first die without perforation, while bonding pad interfaces are positioned at the top surface to enable flexible bonding to different second dies, eliminating the need for complex lateral routing around memory banks.
Data Source
AI summary
Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.