Stacked IC Die Interconnection via Configurable TSV Mapping
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Solution Overview
Problem
The challenge in stacked integrated circuit (IC) die packaging is the alignment of connection sites, particularly when IC dies of different sizes and designs need to be connected using through-silicon-vias (TSVs), which requires matching array structures, limiting the selection of compatible dies and increasing production complexity and cost.
Innovation Solution
The solution involves direct coupling of IC dies without an interposer layer, using connection sites with identical patterns on facing surfaces and configurable alignment circuits to route signals between TSVs, allowing for the connection of IC dies with different dimensions through TSVs that extend through the die and conductive vias, enabling flexible stacking and reduced material usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If TSV packaging is used to connect stacked IC dies, then system bandwidth and connection density are improved, but the requirement for matching connection site array structures limits die selection and increases production complexity
Solution Approach 1:
The connection interface is segmented into two independent parts: the physical TSV array structure and the logical connection mapping. The processor die and memory die can have different TSV array configurations, and the system uses software or configuration mechanisms to map logical connection requests to the appropriate physical TSVs, eliminating the requirement for identical array structures while maintaining high bandwidth performance
Solution Approach 2:
The TSV connection system is designed to be universal by supporting multiple die sizes and TSV array configurations through a common interface standard. The system can accommodate different memory capacities and processor configurations without requiring custom interposer substrates, reducing production complexity while maintaining adaptability
2Adaptability or versatility
If an interposer substrate is used to connect processor IC die to memory IC die, then compatibility between different die sizes is improved, but material cost and design complexity increase
Solution Approach 1:
The interposer substrate function of providing compatibility is extracted and replaced by direct die-to-die bonding with configurable connection mapping. The compatibility function is achieved through software or configuration-based TSV mapping rather than through a physical interposer layer, eliminating the additional material and design complexity while maintaining adaptability between different die sizes
Solution Approach 2:
Instead of using a physical interposer substrate as an intermediary, the system uses a logical intermediary layer in the form of configuration data or software that maps logical connection requests to the appropriate physical TSVs on each die, achieving the same compatibility function without the additional material and design overhead
3Use of energy by moving object
If TSVs are used to connect stacked IC dies, then wiring length and power consumption are reduced, but alignment precision between connection sites is required
Solution Approach 1:
The connection mapping system is made dynamic and configurable rather than fixed. The system can adapt the TSV connection mappings during operation or configuration to accommodate manufacturing variations and alignment tolerances, reducing the stringency of alignment precision requirements while maintaining the power consumption benefits of short TSV connections
Data Source
AI summary
An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.