Stacked Die TSV Timing Calibration for Reliable Signal Capture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increased load on signal paths due to stacking multiple semiconductor dies in portable electronic devices limits the speed of signal transmission, leading to uncertain TSV delay times and potential performance deterioration.
Innovation Solution
A semiconductor device configuration that includes a reference die generating test signals and a target die receiving these signals through TSVs, with a comparison mechanism to determine optimal data transmission conditions by adjusting clock phases and delays to minimize errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor dies are stacked to increase integration, then circuit density is improved, but signal transmission speed deteriorates due to increased load on signal paths
Solution Approach 1:
The patent applies parameter changes by adjusting clock phases and delay times to compensate for TSV-induced signal transmission variations. The system dynamically modifies timing parameters to maintain optimal signal integrity despite the increased load from stacked dies, thereby resolving the contradiction between high circuit density and signal transmission speed.
2Adaptability or versatility
If multiple semiconductor dies are stacked, then integration capacity is improved, but TSV delay time becomes uncertain leading to performance deterioration
Solution Approach 1:
The patent implements feedback mechanisms where the system measures actual signal transmission delays through TSVs and uses this information to adjust clock phases and timing parameters. This closed-loop approach compensates for uncertain TSV delay times, maintaining reliable performance despite variations introduced by stacked die configurations.
Solution Approach 2:
The system dynamically adjusts clock phases and delay times based on measured TSV transmission characteristics. This dynamic adaptation allows the system to optimize signal timing in real-time, compensating for the uncertain and variable delay times introduced by the stacked die architecture, thereby maintaining reliability while achieving high integration capacity.
3Measurement precision
If clock phase adjustment is performed to minimize errors, then data transmission accuracy is improved, but device complexity increases
Solution Approach 1:
The patent employs self-service mechanisms where the system automatically measures TSV delay times and adjusts its own clock phases without external intervention. The semiconductor device performs self-calibration by generating test signals, measuring transmission delays, and autonomously optimizing timing parameters, thereby improving data transmission accuracy while minimizing the complexity of external control mechanisms.
Data Source
AI summary
A semiconductor device according to some example embodiments comprises: a reference die configured to generate a test signal based on a first seed and transmit both an output clock signal and the test signal, and a target die configured to receive the output clock signal as an input clock signal though at least one through-silicon via TSV, capture the test signal as captured data based on the input clock signal, and compare a comparison pattern generated based on the first seed and the captured data.