Stacked Die Through-Dielectric Via Assembly for Thinner 3D Memory
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Solution Overview
Problem
Current methods for assembling 3D stacked memory IC packages, such as through silicon vias (TSVs) and solder microbumps, increase complexity and cost, and result in decreased yields due to the need for extensive interconnect metallization and increased package thickness, limiting the number of tiers that can be included in the stack.
Innovation Solution
The proposed solution involves stacking dies with a trench of dielectric material and a conductive via extending through it, along with conductive pathways made of different materials, which electrically couple the dies directly, reducing the need for extensive interconnects and minimizing connection failures to specific tiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias (TSVs) and solder microbumps are used for assembling 3D stacked memory IC packages, then electrical connection between dies is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the complex interconnect metallization layer from the traditional TSV structure. Instead of using extensive metallization, the invention uses a simplified conductive via filled with conductive material that extends through the dielectric trench, directly connecting the dies without requiring complex metallization schemes.
Solution Approach 2:
The patent employs composite material structures where a dielectric material forms the trench and is combined with conductive material filling the via. This composite approach allows for simplified interconnection while maintaining electrical performance, replacing the need for complex single-material metallization systems.
2Reliability
If through silicon vias (TSVs) and solder microbumps are used for assembling 3D stacked memory IC packages, then electrical connection between dies is achieved, but manufacturing cost increases
Solution Approach 1:
The patent removes the expensive solder microbump and complex metallization components from the assembly process. The simplified conductive via structure reduces material costs and manufacturing steps, making the assembly process more cost-effective while maintaining reliable electrical connections between stacked dies.
3Reliability
If through silicon vias (TSVs) and solder microbumps are used for assembling 3D stacked memory IC packages, then electrical connection between dies is achieved, but manufacturing yield decreases
Solution Approach 1:
The patent eliminates the multiple failure-prone interfaces associated with TSVs and solder microbumps. By using a simplified conductive via that extends continuously through the dielectric trench, the invention reduces the number of potential failure points, thereby improving manufacturing yield and reliability.
4Reliability
If extensive interconnect metallization is used in 3D stacked memory IC packages, then electrical connection between dies is achieved, but package thickness increases
Solution Approach 1:
The patent removes the thick metallization layers required in traditional TSV structures. The conductive via filled with conductive material provides efficient electrical connection with minimal thickness, allowing for thinner package designs while maintaining reliable inter-die connectivity.
5Reliability
If extensive interconnect metallization is used in 3D stacked memory IC packages, then electrical connection between dies is achieved, but the number of tiers that can be included in the stack decreases
Solution Approach 1:
The patent eliminates the bulky metallization structure that limits the number of stackable tiers. The simplified conductive via approach reduces the vertical space required for each interconnection layer, enabling higher tier counts in 3D stacked memory packages without accumulating connection failures.
Data Source
Figure 1A
Figure 1B~1E
Figure 2A~2C
AI summary
Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of dies stacked vertically; a trench of dielectric material extending through the plurality of dies; a conductive via extending through the trench of dielectric material; and a plurality of conductive pathways between the plurality of dies and the conductive via, wherein individual ones of the conductive pathways are electrically coupled to the conductive via and to individual ones of the plurality of dies, and wherein the individual ones of the plurality of conductive pathways have a first portion including a first material and a second portion including a second material different from the first material.