Stacked Die Assembly Using Through-Dielectric Via Interconnects
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Solution Overview
Problem
Current die stacking methods for IC packages involve complex and costly processes with through silicon vias (TSVs) and interconnect metallization, leading to increased thickness and reduced yield due to failure propagation across tiers, limiting the number of stackable tiers and overall performance.
Innovation Solution
The use of a conductive via in a channel of dielectric material adjacent to stacked dies, electrically coupling them, reduces complexity and cost by eliminating the need for TSVs and interconnect metallization at each tier, while maintaining electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias (TSVs) and interconnect metallization are used in die stacking, then electrical connectivity between tiers is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the complex TSV and interconnect metallization processes from each die tier, replacing them with a simplified bonding interface approach where conductive bumps or pads directly connect stacked dies, removing unnecessary intermediate structures
Solution Approach 2:
The patent segments the interconnection function into separate bonding interfaces at each die stack level, allowing independent optimization of each interface rather than requiring through-silicon vias that penetrate entire die stacks, thereby reducing overall complexity
2Reliability
If through silicon vias (TSVs) and interconnect metallization are used in die stacking, then electrical connectivity between tiers is achieved, but manufacturing cost increases
Solution Approach 1:
The patent removes the expensive TSV formation and multi-layer interconnect metallization processes from the manufacturing flow, replacing them with simpler direct bonding techniques that use conductive bumps or pads, significantly reducing material and process costs
Solution Approach 2:
The patent employs cost-effective bonding materials such as solder bumps or simple conductive pastes instead of expensive TSV fill materials and complex interconnect metallization layers, achieving acceptable connectivity at lower cost
3Reliability
If through silicon vias (TSVs) and interconnect metallization are used in die stacking, then electrical connectivity between tiers is achieved, but package thickness increases
Solution Approach 1:
The patent eliminates the thick TSV structures and multiple interconnect metallization layers from each die tier, replacing them with thin bonding interfaces that achieve electrical connectivity with minimal vertical space, thereby reducing overall package thickness
Data Source
AI summary
Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of dies stacked vertically; a trench of dielectric material extending through the plurality of dies; a conductive via extending through the trench of dielectric material; and a plurality of conductive pathways between the plurality of dies and the conductive via, wherein individual ones of the conductive pathways are electrically coupled to the conductive via and to individual ones of the plurality of dies, and wherein the individual ones of the plurality of conductive pathways have a first portion including a first material and a second portion including a second material different from the first material.