Stacked Die Wire Bond Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional stacked microelectronic packages face challenges with complexity, cost, thickness, and testability, particularly in incorporating multiple semiconductor chips for memory applications like flash memory, requiring improved reliability, thinness, and economical manufacturing.
Innovation Solution
The solution involves stacking microelectronic elements with parallel front surfaces, using wire bonds electrically coupled to package contacts, and forming an encapsulation region over edge surfaces to create a compact, reliable, and testable package configuration, with additional package contacts on major and peripheral surfaces for enhanced interconnectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple semiconductor chips are stacked within a package to save space, then the surface area occupied by the package is reduced, but the package complexity increases
Solution Approach 1:
The patent segments the interconnection function into multiple independent wire bonds, each connecting specific contacts between stacked chips. This modular approach allows each chip in the stack to be independently connected and tested, reducing overall package complexity while maintaining compact stacking.
Solution Approach 2:
The patent introduces an encapsulation region as an intermediary structure that houses and organizes the wire bonds between stacked chips. This intermediary element simplifies the overall package structure by containing the interconnection complexity within a defined boundary, making the stacked package more manageable despite the increased complexity from multiple chips.
2Length of stationary object
If conventional stacked packages are used to reduce package thickness, then space is saved, but testability deteriorates
Solution Approach 1:
The patent performs wire bonding and encapsulation of individual chip stacks before final package assembly. This preliminary action allows each stack to be pre-tested and validated independently, improving testability while maintaining thin package thickness. The encapsulation region is formed early in the process, enabling subsequent testing through the encapsulant.
Solution Approach 2:
The patent provides localized access points and test contacts at specific regions of the encapsulated stack, allowing testing to be performed on specific areas without requiring complete package disassembly. This localized approach to testability maintains thin overall package thickness while enabling effective testing.
3Ease of manufacture
If wire bonds are used to electrically interconnect stacked chips, then manufacturing cost is reduced, but the package thickness increases
Solution Approach 1:
The patent nests the wire bonds within the encapsulation region, which itself is contained within the overall package structure. This nested arrangement allows wire bonds to be accommodated in a compact volume, reducing the thickness increase that would otherwise result from using wire bonds for interconnection.
Solution Approach 2:
The patent routes wire bonds through three-dimensional space within the encapsulation region, utilizing vertical and lateral dimensions efficiently. This multi-dimensional routing allows wire bonds to connect stacked chips without simply increasing package thickness linearly, as the bonds can traverse multiple dimensions within the encapsulated volume.
Data Source
AI summary
A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.