Stacked Die Wire Bond Interconnects via Interior Metal Layers
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Solution Overview
Problem
Conventional integrated circuit (IC) packages with stacked dies experience increased resistance and inductance due to long wire bond connections, leading to energy loss and signal degradation, particularly in mobile computing devices where minimal latency is crucial.
Innovation Solution
The IC package employs a metallization structure with stacked die wire bond connections that route through an interior metal layer, utilizing vias to shorten the connection length and reduce resistance and inductance, thereby improving performance and reducing energy loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bond connections are used to connect stacked IC dies to the substrate, then the IC package can be manufactured with conventional processes, but the connection length increases resulting in increased resistance and inductance
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical routing through interior metal layers. Wire bonds connect to contact pads on the substrate surface, which then route through vias to interior metal layers (e.g., M1, M2) that provide vertical interconnect paths. This dimensional change allows signals to travel through the substrate thickness rather than along the surface, effectively shortening the current path and reducing resistance and inductance while maintaining conventional wire bond manufacturing processes.
2Ease of manufacture
If wire bond connections are used to connect stacked IC dies, then the connection can be established with conventional bonding processes, but the connection length increases resulting in increased inductance
Solution Approach 1:
The patent utilizes vertical routing through interior metal layers to reduce the horizontal distance that wire bonds must travel. By routing through the substrate's interior via vias connected to multiple metal layers, the current path is shortened from a long lateral path to a more direct vertical path, reducing parasitic inductance and improving signal quality while maintaining compatibility with conventional wire bond bonding processes.
3Device complexity
If long wire bond connections are used in stacked die packages, then conventional packaging methods can be employed, but resistance increases leading to voltage drop and signal degradation
Solution Approach 1:
The patent implements a three-dimensional interconnect architecture where contact pads on the substrate surface connect through vias to interior metal layers that provide vertical routing paths. This allows current to flow vertically through the substrate rather than traveling long horizontal paths, significantly reducing resistance and voltage drop. The solution maintains relatively simple packaging structure by utilizing the substrate's existing multi-layer metallization capability rather than adding complex external interconnect structures.
Data Source
AI summary
An integrated circuit (IC) package with stacked die wire bond connections has two stacked IC dies, where a first die couples to a metallization structure directly and a second die stacked on top of the first die connects to the metallization structure through wire bond connections. The IC dies are coupled to one another through an interior metal layer of the metallization structure. Vias are used to couple to the interior metal layer.