Stacked Die Package Layout Without TSVs for Thin High-I/O Bonding
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Solution Overview
Problem
Existing electronic packages with stacked substrates or dies face limitations in flexibility, thickness, and footprint due to bonding techniques, wiring requirements, and manufacturing processes, such as minimum die thickness in wire bonding and high costs in through silicon via (TSV) stacking.
Innovation Solution
The implementation of face-to-face wafer-to-wafer bonding with thinned and stacked wire bonding, which reduces die thickness to about 10 um, eliminates the need for TSVs, and accommodates large numbers of I/O connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding techniques are used for stacked substrates, then electrical connections can be established, but the die thickness is limited to a minimum thickness
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked architecture, allowing electrical connections to be made in the vertical dimension through face-to-face bonding interfaces, thereby overcoming the thickness limitations of traditional wire bonding while maintaining connection reliability
Solution Approach 2:
The patent divides the package into multiple thin die layers (first substrate, second substrate, third substrate) that are bonded face-to-face, with each layer being thinner than traditional single-die implementations, thereby achieving overall flexibility while maintaining electrical connectivity through segmented bonding interfaces
2Reliability
If through silicon via (TSV) stacking is used, then vertical electrical connections can be achieved, but manufacturing costs increase significantly
Solution Approach 1:
The patent extracts and eliminates the need for expensive TSV formation processes by using alternative face-to-face bonding techniques with bonding pads and interconnect structures that achieve vertical electrical connections through substrate bonding interfaces rather than through-silicon vias, thereby maintaining connection reliability while reducing manufacturing complexity and cost
Solution Approach 2:
The patent employs cost-effective bonding structures such as bonding pads, adhesive layers, and wire bonds at the substrate interfaces instead of expensive TSV processes, using simpler, more economical materials and methods to achieve the same electrical interconnection function
3Reliability
If traditional stacked substrate packaging is used, then electrical connections are established, but the package footprint and flexibility are limited
Solution Approach 1:
The patent moves electrical connections from the planar dimension to the vertical dimension through stacked substrate architecture, allowing I/O contacts to be positioned on the same plane as bonding interfaces, thereby reducing the horizontal footprint while maintaining connection reliability through three-dimensional stacking
Solution Approach 2:
The patent introduces flexibility to the stacked package structure by using thin die layers and flexible bonding interfaces that allow the package to bend and conform to different mounting surfaces, transforming the rigid traditional stack into a dynamic, adaptable structure
4Adaptability or versatility
If more I/O connections are added to stacked packages, then connectivity increases, but wiring requirements and complexity increase
Solution Approach 1:
The patent utilizes the vertical stacking dimension to provide multiple bonding interfaces between substrates, allowing a large number of I/O connections to be established through face-to-face bonding pads without requiring complex lateral wiring routes, thereby increasing connectivity while maintaining wiring simplicity through three-dimensional interconnection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves double density in chip packages, reduces manufacturing costs, and allows for thinner, more flexible electronic packages with improved I/O connectivity.
Implementation Method 1
face-to-face wafer-to-wafer bonding
Data Source
AI summary
A package includes a first chip stack. The first chip stack includes a first chip including first bonding structures, a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures, and a first electrical contact on the second chip. At least a portion of the first electrical contact does not overlap with the first chip in a plan view.