Stacked Dielectric Layer for Contact Plug Etching
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Solution Overview
Problem
The existing method of fabricating semiconductor structures with contact plugs faces challenges due to over etching issues in the dielectric layer, leading to damage in the peripheral circuit region, caused by the large thickness of the dielectric layer, which affects the accuracy of the etching process.
Innovation Solution
A method involving a stacked dielectric layer with two first dielectric layers and a second dielectric layer, where the first dielectric layers are etched selectively to expose the second dielectric layer, preventing over etching by using different etching rates and allowing for precise planarization and contact plug formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a single thick dielectric layer is used to cover the peripheral circuit region, then the capacitor height can be increased to gain more capacitance, but the etching accuracy deteriorates causing over etching problems
Solution Approach 1:
The single thick dielectric layer is segmented into a stacked structure comprising a first dielectric layer, a second dielectric layer, and a third dielectric layer. This segmentation allows the etching process to be divided into multiple stages, with each layer being etched separately to achieve precise control and prevent over etching while maintaining the required total thickness for capacitor height.
Solution Approach 2:
Different dielectric layers are used with different material properties and etching rates. The first, second, and third dielectric layers have distinct local qualities that enable selective etching. This allows the etching process to stop at precise depths for each layer, ensuring manufacturing precision while accommodating the overall thickness requirement.
2Quantity of substance
If a large thickness dielectric layer is used, then the capacitor capacitance increases, but the elements in the peripheral circuit region are damaged due to over etching
Solution Approach 1:
The thick dielectric layer is divided into multiple thinner layers (first, second, and third dielectric layers) stacked together. Each layer can be etched with controlled depth, preventing excessive etching that would damage peripheral circuit elements while maintaining the total thickness needed for adequate capacitance.
Solution Approach 2:
The dielectric layers are prepared in a stacked structure before the etching process, with each layer designed to be etched to a specific depth. This preliminary structuring ensures that the etching process stops at appropriate boundaries, protecting underlying elements from damage while achieving the required capacitance.
3Ease of manufacture
If a single dielectric layer is etched through, then the contact plug can be formed, but the etching process lacks precision causing over etching
Solution Approach 1:
The etching process is segmented into multiple stages corresponding to each dielectric layer. The first dielectric layer is etched to a first depth, the second dielectric layer to a second depth, and the third dielectric layer to a third depth. This segmentation provides precise depth control at each stage, ensuring manufacturing precision while maintaining ease of contact plug formation.
Solution Approach 2:
Each dielectric layer has distinct material properties that enable selective etching with different rates and depths. This local quality difference allows the etching process to precisely control the depth for each layer, achieving both ease of manufacture and high precision in contact plug formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents over etching and damage to the peripheral circuit region by using a multiple-layered dielectric structure, ensuring accurate etching and maintaining the integrity of the capacitor structure, while also reducing interface stresses.
Implementation Method 1
the first dielectric layers are etched selectively to expose the second dielectric layer, preventing over etching by using different etching rates
Data Source
AI summary
A semiconductor structure having a contact plug includes a substrate. A memory cell region and a peripheral circuit region are defined on the substrate. At least one memory cell is disposed on the substrate within the memory cell region. The memory cell includes a transistor and a capacitor structure. A first planar stacked dielectric layer covers the peripheral circuit region. The first planar stacked dielectric layer includes two first dielectric layers and a second dielectric layer. The first dielectric layer at the bottom of the first planar stacked dielectric layer extends to the memory cell region and covers the capacitor structure. A contact plug is disposed at the peripheral circuit region and penetrates the first planar stacked dielectric layer.