3D Stacked Diffusion Break Layout for Transistor Stress Control
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Solution Overview
Problem
Existing diffusion break structures in semiconductor devices struggle to effectively isolate and control stress in transistors, particularly in multi-stack semiconductor devices, leading to inefficiencies in drive current performance.
Innovation Solution
Implementing diffusion break structures with different material compositions and/or physical dimensions to isolate and control stress in transistors, specifically using silicon nitride for compressive stress control and tonen silazene for tensile stress control in PFETs and NFETs, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single diffusion break structure is used to isolate transistors, then device density is improved, but stress control capability deteriorates
Solution Approach 1:
The diffusion break structure is segmented into multiple portions (first diffusion break structure and second diffusion break structure) with different material compositions. The first portion uses silicon nitride for compressive stress control while the second portion uses silicon oxide for isolation, allowing simultaneous optimization of both device density and stress control capability through functional segmentation of the diffusion break structure.
2Reliability
If different material compositions are used for stress control, then drive current performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the isolation function and stress control function into a single integrated diffusion break structure by forming different material portions (silicon nitride and silicon oxide) within the same structural footprint. This combining of functions reduces manufacturing complexity compared to using separate structures, while still achieving improved drive current performance through appropriate stress control.
3Reliability
If silicon nitride is used for compressive stress control in PFETs, then drive current performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by selecting specific material compositions (silicon nitride for compressive stress, silicon oxide for isolation) with well-established deposition parameters and characteristics. By changing the material composition parameter to use materials with known and controllable deposition properties, the patent achieves improved drive current performance while managing manufacturing precision requirements through the use of mature fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances drive current performance by effectively controlling stress in multi-stack semiconductor devices, improving device isolation and density.
Implementation Method 1
the first diffusion break structure may be formed of a first material composition favorable to compressive stress control of PFETs
Implementation Method 2
the second diffusion break structure may be formed of a second material composition favorable to tensile stress control of NFETs
Data Source
AI summary
A multi-stack semiconductor device formed to cover a plurality of gate pitches includes: a 1st transistor; a 2nd transistor formed at a right side of the 1st transistor, and isolated from the 1st transistor by a 1st portion of a diffusion break structure; a 3rd transistor formed vertically above or below the 1st transistor; and a 4th transistor formed at a right side of the 3rd transistor, and isolated from the 3rd transistor by a 2nd portion of the diffusion break structure, wherein the 1st portion and the 2nd portion of the diffusion break structure are formed of different material compositions or have different physical dimensions.