Stacked DIMM Interface Circuit Eliminates Bus Turnaround Latency
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Solution Overview
Problem
Memory systems face limitations in command scheduling and data transfer bandwidth due to inter-device and intra-device command scheduling constraints, leading to latency and incompatibility issues with existing memory controllers, particularly in high-speed systems like FBDIMMs.
Innovation Solution
An interface circuit that combines data bursts from multiple memory devices into a contiguous burst, using emulation and command translation logic to eliminate clock-to-data phase delays and re-drive data bursts, allowing seamless switching without idle bus cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FBDIMM approach is used to assemble data from multiple memory devices, then data assembly capability is achieved, but significant latency is introduced
Solution Approach 1:
The patent applies preliminary action by pre-assembling data bursts from multiple memory devices into contiguous bursts at the memory device level before transmission to the controller. The interface circuit combines data bursts from multiple devices in advance, eliminating the need for the controller to perform time-consuming assembly operations after data retrieval, thus reducing overall system latency while maintaining data assembly capability
2Productivity
If FBDIMM-type memory devices are implemented, then enhanced memory performance is achieved, but backward compatibility with existing memory controllers is lost
Solution Approach 1:
The patent introduces an interface circuit as an intermediary between the memory devices and the existing memory controller. This interface circuit handles the complex data assembly and timing operations, allowing the memory devices to operate in high-performance FBDIMM mode while presenting a standard interface to the controller. This mediator enables enhanced memory performance without sacrificing backward compatibility, as the controller sees only standard memory operations
3Productivity
If data bursts from multiple memory devices are combined into contiguous bursts, then bandwidth is increased, but interface circuit complexity is increased
Solution Approach 1:
The patent applies segmentation by dividing the memory system into distinct functional components: individual memory devices that generate data bursts, an interface circuit that combines these bursts, and a controller that issues commands. By segmenting the data assembly function into a dedicated interface circuit, the system achieves contiguous data bursts and increased bandwidth, while the complexity is localized to the interface circuit rather than distributed throughout the entire memory system
Data Source
AI summary
One embodiment of the present invention sets forth an interface circuit configured to combine time staggered data bursts returned by multiple memory devices into a larger contiguous data burst. As a result, an accurate timing reference for data transmission that retains the use of data (DQ) and data strobe (DQS) signals in an infrastructure-compatible system while eliminating the cost of the idle cycles required for data bus turnarounds to switch from reading from one memory device to reading from another memory device, or from writing to one memory device to writing to another memory device may be obtained, thereby increasing memory system bandwidth relative to the prior art approaches.