Stacked Diode-String ESD Structure for Compact Power Semiconductors

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Solution Overview

Problem

Semiconductor power devices are susceptible to damage from electrostatic discharge events, which can break down the gate oxide layer and cause high leakage or burn-out due to instantaneous high current and voltage.

Innovation Solution

An electrostatic discharge protection structure is implemented using a stacking design with multiple diode strings arranged in parallel, including first and second trench structures and diode strings, which are connected in parallel and separated by oxide layers, to provide enhanced protection without occupying additional circuit area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple diode strings are arranged in parallel to enhance ESD protection capability, then the ESD protection capability and current conduction capability are improved, but the circuit area occupied increases

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar arrangement of diode strings to a three-dimensional stacked configuration. Multiple diode strings are arranged vertically in layers, with upper diode strings positioned above lower diode strings through vertical stacking. This spatial reorganization allows multiple ESD protection paths to coexist within a compact footprint, significantly improving ESD protection capability without proportionally increasing the circuit area occupied.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the number of diode strings per unit area is increased to improve ESD protection, then the ESD protection capability is enhanced, but the device complexity increases

Engineering Contradiction:
ImproveESD protection capabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a nested stacking structure where multiple diode strings are vertically integrated in a compact configuration. Upper diode strings are positioned above lower diode strings, with shared support structures and interconnected electrode systems. This nesting approach allows multiple ESD protection elements to be densely packed without linearly increasing interconnection complexity, as common electrodes and support structures serve multiple diode strings simultaneously.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Productivity

If a compact design with higher diode string density is implemented, then the current conduction capability is improved, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvecurrent conduction capabilityVSAvoidmanufacturing precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent divides the ESD protection structure into modular diode string units that can be independently formed and then vertically stacked. Each diode string is a discrete module with standardized electrodes and connections. This segmentation allows for modular manufacturing where precision requirements are localized to each module rather than the entire structure, facilitating higher density packing while maintaining manufacturability through repeated modular assembly.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4598307A1Electrostatic discharge protection structure, semiconductor power device and manufacturing method thereof
Publication Date: 2025.08.06 DIODES INC
  • EP4598307A1 patent drawingFigure 1
  • EP4598307A1 patent drawingFigure 2
  • EP4598307A1 patent drawingFigure 3A~3B

AI summary

An electrostatic discharge protection structure in a semiconductor device includes a first trench structure including a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure. A second trench structure includes a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure. A first diode string is disposed between the first trench structure and the second trench structure and adjoins the first polysilicon structure and the second polysilicon structure. A first spacing oxide layer is disposed on the first diode string. A second diode string is disposed on the first spacing oxide layer and connected in parallel with the first diode string. Each of the first and the second diode strings includes first doped regions and second doped regions disposed alternately. APN junction is formed at an interface between each first doped region and an adjacent second doped region.