Stacked Display Transistor Layout With Shielded Coupling Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Transistor overcrowding and coupling between transistors in display devices due to high integration for higher quality and resolution, leading to increased area requirements and potential electrical interference.
Innovation Solution
A display device design with vertically stacked transistors, utilizing a shield pattern to prevent coupling by applying different direct current voltages and ensuring the second transistor's channel region does not overlap with the shield pattern, along with a conductive pattern electrically connected to the second transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If transistors are highly integrated to achieve higher quality and resolution displays, then display quality and resolution are improved, but transistor overcrowding and coupling between transistors occur
Solution Approach 1:
The patent transitions from planar transistor arrangement to three-dimensional vertical stacking, where the second transistor is disposed directly on the first transistor in the thickness direction. This dimensional change allows higher integration without increasing planar area, thereby improving display resolution while maintaining transistor spacing through the insulating layer to prevent coupling.
Solution Approach 2:
The patent introduces a shield pattern as an intermediary element disposed between the first and second transistors. This shield pattern, connected to a fixed potential, acts as an electromagnetic shield to prevent coupling between the vertically stacked transistors, enabling high integration while eliminating the harmful coupling effect.
2Measurement precision
If transistors are disposed in a limited area to achieve high integration, then display resolution is improved, but transistor overcrowding occurs
Solution Approach 1:
The patent utilizes vertical stacking in the thickness direction to achieve high integration within a limited planar area. By arranging transistors in multiple layers rather than spreading them out planarly, the design achieves higher resolution while maintaining simpler routing and connection paths compared to dense planar arrangements.
3Object-affected harmful factors
If shield pattern is added to prevent transistor coupling, then coupling is prevented, but device complexity increases
Solution Approach 1:
The patent merges the shield pattern formation with the existing transistor manufacturing process by forming the shield pattern on the same substrate using the same thin-film deposition techniques. The shield pattern is integrated into the vertical stack structure, sharing layers and processes with the transistor components, thereby minimizing additional process steps and reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents transistor coupling, reduces the circuit area, and enables higher resolution displays by optimizing transistor arrangement.
Implementation Method 1
a first shield pattern disposed on the first insulating layer and to which a direct current voltage is applied
Data Source
AI summary
A display device includes a substrate including a display area and a peripheral area surrounding the display area, a first transistor disposed in the peripheral area of the substrate and including a first active layer having a first channel region and a first gate electrode, a first insulating layer disposed on the first transistor, a first shield pattern disposed on the first insulating layer and to which a direct current voltage is applied, a second insulating layer covering the first shield pattern, and a second transistor directly disposed on the second insulating layer and including a second active layer having a second channel region spaced apart from the first shield pattern in a plan view and a second gate electrode.