Head-Mounted Display Stacked Substrates for Interference-Free Wiring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing head-mounted display devices face challenges in achieving high-resolution images due to the limitations of current display technologies, particularly in efficiently connecting multiple semiconductor substrates without interference, which affects manufacturing yield and performance.
Innovation Solution
The use of a micro display device with a layout design that includes two different single crystal semiconductor substrates, featuring efficient connection wirings between them, and a connection line layer with conductive vias and bridge lines to facilitate electrical connections, allowing for a high-resolution image display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor substrates are connected using conventional wiring methods, then electrical connections can be established, but wiring interference occurs and manufacturing yield decreases
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked wiring architecture. Multiple semiconductor substrates are vertically stacked with connection lines extending through interlayer insulating layers via through-holes, enabling electrical connections in the vertical dimension while preventing lateral wiring interference.
Solution Approach 2:
The patent introduces interlayer insulating layers with through-holes as intermediary structures. These through-holes serve as conduits for connection lines to pass through isolated insulating barriers, enabling electrical connections between stacked substrates while the insulating material prevents short circuits and interference.
2Manufacturing precision
If display resolution is increased for high-quality images, then image quality improves, but device size and complexity increase
Solution Approach 1:
The patent divides the display device into multiple independent semiconductor substrates stacked vertically. Each substrate contains a portion of the pixel array, allowing high-resolution imaging to be achieved through vertical stacking rather than expanding a single planar substrate, thus managing complexity through modular segmentation.
Solution Approach 2:
The patent achieves high display resolution by extending the pixel array into the vertical dimension through stacked substrates. This three-dimensional arrangement allows more pixels to be packed into a compact footprint without proportionally increasing lateral device complexity.
3Area of moving object
If substrate size is reduced for compact head-mounted display, then device compactness improves, but wiring space and connection reliability deteriorate
Solution Approach 1:
The patent compensates for reduced substrate area by utilizing the vertical dimension for connections. Through-holes penetrating interlayer insulating layers provide reliable electrical pathways between stacked substrates, maintaining connection reliability despite smaller lateral substrate dimensions.
Solution Approach 2:
The patent segments the display into multiple smaller substrates stacked vertically, each with simplified wiring requirements. This segmentation allows compact substrate areas while maintaining connection reliability through vertical stacking and dedicated through-hole connections.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A display device and a head mounted display device are provided. A display device includes: a first single crystal semiconductor substrate on which a plurality of pixel circuits arranged along a first direction and a second direction intersecting the first direction is located, the plurality of pixel circuits including a first transistor; a second single crystal semiconductor substrate on the first single crystal semiconductor substrate, the second single crystal semiconductor substrate on which a plurality of sub-pixels including a plurality of light emitting elements and arranged along the first direction and the second direction is located; and a connection line layer between the plurality of light emitting elements and the first single crystal semiconductor substrate and including a plurality of bridge lines, each of the plurality of bridge lines electrically connected to one of the plurality of pixel circuits and one of the plurality of sub-pixels.