Stacked Display Wiring Layout for High-Pixel-Density Panels
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Solution Overview
Problem
The increase in the number of pixels in display devices, such as head-mounted displays, leads to an increase in the number of signal lines, which in turn increases the device size and area, posing a challenge in efficiently arranging these signal lines.
Innovation Solution
A display device is designed with a novel structure that includes transistors using oxide semiconductors for the channel, featuring multiple gate electrodes and wirings arranged in different layers, allowing for efficient arrangement of signal lines by overlapping and positioning them at specific distances in a plan view.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels is increased to achieve high-definition display, then the image quality is improved, but the number of signal lines increases and the device size increases
Solution Approach 1:
The patent applies three-dimensional stacking of transistor layers to reduce the planar area occupied by signal lines. Multiple gate electrodes are arranged in different layers (first gate electrode in one layer, second gate electrode in another layer), allowing signal lines to be routed vertically through the substrate rather than spreading out horizontally, thus reducing device size while maintaining high pixel density
Solution Approach 2:
The patent implements nested wiring structures where multiple wirings are positioned at different depths within the substrate. The first wiring, second wiring, and third wiring are arranged in overlapping configurations in plan view but separated in the vertical dimension, creating a nested arrangement that efficiently packs signal lines without increasing the device footprint
2Measurement precision
If more signal lines are added to support higher pixel density, then the display resolution is improved, but the layout complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the signal line routing into multiple segments across different layers. The first wiring handles certain signal routes, the second wiring handles other routes, and the third wiring (formed in the same layer as source or drain electrodes) handles additional routes, segmenting the complex routing task into manageable layers that can be manufactured separately and stacked
Solution Approach 2:
By transitioning from two-dimensional planar routing to three-dimensional stacked routing, the patent reduces layout complexity. The first gate electrode and second gate electrode are positioned in different layers, allowing signal lines to cross underneath each other vertically rather than requiring complex planar routing around each other, thereby simplifying the overall layout design
Data Source
AI summary
A display device includes a first transistor including a first material as a semiconductor material and including a first gate electrode, a second transistor including a second material as a semiconductor material different from the first material and including a second gate electrode arranged in a different layer from the first gate electrode, a first wiring arranged in the same layer as the first gate electrode, a second wiring arranged in the same layer as the second gate electrode, and a third wiring formed in the same layer as a source electrode or a drain electrode of the second transistor and different from the first wiring and the second wiring. The first wiring, the second wiring and the third wiring overlap in a plan view.