Stacked Transistors With Diverse Fin Geometry for Thermal Efficiency
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Solution Overview
Problem
Existing semiconductor fin architectures face challenges in scaling and performance issues due to uniform fin widths across different layers, leading to suboptimal electrical, thermal, and mechanical characteristics in stacked transistor architectures.
Innovation Solution
Employing diverse fin geometries, including varying fin widths and heights across different layers, particularly for NMOS and PMOS transistors, using techniques such as aspect ratio trapping (ART) and selective etching to form fins with different semiconductor materials, allowing for improved electrical and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform fin widths are used across all layers, then manufacturing process is simpler, but electrical and thermal performance deteriorates
Solution Approach 1:
The patent applies local quality by assigning different fin widths to different device layers. Specifically, first device layers (e.g., NMOS) have first fin widths while second device layers (e.g., PMOS) have second fin widths that are different from the first. This allows each layer to be optimized for its specific electrical and thermal requirements, with wider fins providing better thermal dissipation and electrical performance where needed, while maintaining manufacturing feasibility through selective etching processes.
2Reliability
If diverse fin geometries are employed, then electrical and thermal performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the fin structure into different width regions corresponding to different device layers. By dividing the unified fin into segment-specific width portions, each segment can be independently optimized for its device type (NMOS or PMOS). The segmentation is achieved through selective etching that removes material from specific depth ranges, creating the diverse geometries needed for optimal electrical and thermal performance without requiring complete redesign of the manufacturing process.
Solution Approach 2:
The patent changes the geometric parameters of the fin structure by creating different fin widths at different vertical levels. The first fin width is maintained for first device layers while a second, different fin width is created for second device layers. This parameter change is accomplished through controlled selective etching that modifies the fin geometry in specific depth ranges, allowing optimization of electrical and thermal characteristics for different device types within the same stacked architecture.
3Reliability
If selective etching is used to create diverse fin geometries, then device performance is optimized, but process steps increase
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial layer with specific etch selectivity before creating the diverse fin geometries. This sacrificial layer is deposited and patterned in advance to define the regions where selective etching will later create the different fin widths. By preparing this template structure beforehand, the subsequent selective etching process can efficiently create the optimized geometries without requiring multiple separate patterning steps, thus maintaining fabrication efficiency while achieving device performance optimization.
Data Source
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Figure 1C
AI summary
An integrated circuit structure includes: a top semiconductor fin extending in a length direction; a bottom semiconductor fin extending in the length direction, the bottom semiconductor fin being under and vertically aligned with the top semiconductor fin; a top gate structure in contact with a portion of the top semiconductor fin; top source and drain regions each adjacent to the portion of the top semiconductor fin; a bottom gate structure in contact with a portion of the bottom semiconductor fin; and bottom source and drain regions each adjacent to the portion of the bottom semiconductor fin. The portion of the top semiconductor fin is between the top source region and the top drain region. The portion of the bottom semiconductor fin is between the bottom source and drain regions. Heights, widths, or both the heights and widths of the portions of the top and bottom semiconductor fins are different.