Stacked Digital Power Amplifier Feedback for High Supply Voltage
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Solution Overview
Problem
Conventional digital power amplifiers (DPAs) face limitations in output power due to low supply voltage and reliability issues with transistor stress, particularly in switched capacitor (SC-DPA) topologies, which restrict their performance in applications requiring higher transmit power.
Innovation Solution
A dual feedback topology is introduced in DPA architectures, incorporating a first capacitive feedback path for self-generated DC bias voltages and a second voltage stabilizing feedback path to manage transistor stress and dynamic effects, allowing operation with high supply voltages beyond twice the maximum transistor rating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional SC-DPA topology is used, then power efficiency is improved, but output power is limited due to low supply voltage
Solution Approach 1:
The power amplifier output stage is segmented into multiple stacked transistor devices (first DPA device and second DPA device) connected in series between the supply voltage node and ground. This segmentation allows the supply voltage to be distributed across multiple devices, enabling operation at higher supply voltages (beyond twice the maximum transistor rating) while maintaining device reliability, thereby increasing output power without sacrificing the efficiency benefits of the SC-DPA topology
2Power
If high supply voltage is applied to increase output power, then output power is improved, but transistor stress and reliability issues worsen
Solution Approach 1:
The high supply voltage is segmented across multiple stacked transistor devices, with each device experiencing only a portion of the total voltage stress. The feedback capacitor network further segments and controls the voltage distribution, ensuring that no single transistor exceeds its maximum voltage rating even when operating at supply voltages beyond twice the maximum transistor rating
Solution Approach 2:
A feedback mechanism using capacitors is implemented to dynamically control the voltage distribution across the stacked transistor devices. The feedback capacitor network monitors and adjusts the voltage at intermediate nodes, preventing excessive voltage stress on individual transistors while enabling operation at high supply voltages for increased output power
3Adaptability or versatility
If additional DC-DC converters are added to increase supply voltage range, then supply range is improved, but device complexity increases
Solution Approach 1:
The stacked transistor configuration with feedback capacitor network enables the power amplifier to self-regulate and operate across a wide supply voltage range without requiring external DC-DC converters. The inherent device structure and feedback mechanism automatically adapt to different supply voltages, eliminating the need for additional voltage conversion circuitry and reducing overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances output power, improves efficiency, reduces dynamic effects, and ensures long-term reliability by minimizing transistor stress and eliminating the need for additional DC-DC converters, thus optimizing power and efficiency trade-offs.
Implementation Method 1
a feedback capacitor network having a first feedback capacitor and a second feedback capacitor, each having a respective capacitive node coupled to a gate of a respective one of the stacked DPA devices
Data Source
AI summary
Techniques are disclosed to instruct how a switched capacitor digital power amplifier (PA) is configured to operate using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg. The digital PA has a topology that comprises a dual-feedback capacitive path that comprises a capacitive divider and a voltage stabilizing feedback path to selectively couple the capacitive divider to DC bias voltages.