Stacked DRAM Bit Cell With Vertical Word Lines
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Solution Overview
Problem
Current DRAM technologies face challenges in reducing memory cell area without compromising performance and manufacturability, particularly due to the limitations of capacitor design and increased geometrical complexity.
Innovation Solution
A memory device with a stacked configuration of bit cells, where each bit cell includes a write transistor and a read transistor, with a parasitic capacitive coupling for charge storage, and vertically extending word lines and horizontally isolated bit lines, allowing for efficient area utilization and improved access to terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitor physical dimensions are reduced to increase circuit density, then memory cell area is reduced, but capacitance is reduced and geometrical complexity increases
Solution Approach 1:
The patent transitions from planar capacitor design to three-dimensional stacked capacitor structures. Multiple capacitor plates are arranged vertically with alternating conductive and dielectric layers, enabling increased capacitance within a smaller footprint by utilizing the vertical dimension rather than expanding horizontally.
Solution Approach 2:
The capacitor structure employs nested concentric rings where inner conductive plates are surrounded by outer conductive plates, with dielectric materials filling the spaces between them. This nested configuration maximizes the overlapping area between plates while maintaining a compact circular footprint.
2Productivity
If capacitor physical dimensions are reduced to increase circuit density, then memory cell area is reduced, but geometrical complexity increases
Solution Approach 1:
The capacitor is divided into multiple discrete segments or plates arranged in a stacked configuration. Each plate pair forms an independent capacitive element, and the overall capacitor is constructed by stacking these segmented elements vertically, simplifying the manufacturing process while achieving high density.
Solution Approach 2:
The stacked capacitor structure serves multiple functions simultaneously: it provides high capacitance value, achieves area reduction, and maintains compatibility with standard semiconductor fabrication processes. The same layered structure also provides electrical isolation between adjacent bit cells.
3Area of stationary object
If stacked configuration is used to reduce memory cell area, then area efficiency is improved, but access to terminals becomes more complex
Solution Approach 1:
Word lines are extended vertically through the stacked structure to reach write transistors in upper bit cells, while bit lines remain in the planar domain. This three-dimensional wiring approach allows efficient terminal access without significantly increasing the lateral footprint of the memory cell.
Solution Approach 2:
Multiple word lines from different bit cells are merged into common vertical interconnect structures that traverse through the stacked layers. This sharing of vertical interconnects reduces the overall wiring complexity and allows efficient addressing of multiple stacked bit cells using fewer external connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances area efficiency and scalability, maintaining performance while reducing the memory cell area, and allows for more efficient data storage and retrieval operations.
Implementation Method 1
A first source/drain terminal of the write transistor can be connected to a gate of the read transistor to form a storage node of the bit cell
Data Source
AI summary
A memory device configured as a dynamic random access memory is provided, comprising a first semiconductor device layer comprising a first bit cell and a second semiconductor device layer comprising a second DRAM bit cell. Further, at least one of a first and second interconnecting structure is provided, the first interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a write word line common to the gate terminal of the write transistors of the first and second bit cells, and the second interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a read word line common to a first source/drain terminal of the read transistors of the first and second bit cells.