Stacked DRAM Block Copy via Time-Division Direct Channels
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Solution Overview
Problem
Existing memory systems face inefficiencies in data access and latency due to the need for data to pass through a central processing element, which increases communication time and latency.
Innovation Solution
Implementing direct memory channels using time-division multiplexing to directly connect DRAM dies within a stack, allowing each die to communicate at its core frequency without passing through a central processing element, thereby reducing latency and increasing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is transferred through the custom die in a stacked memory system, then data access between memory devices is achieved, but latency increases and bandwidth decreases
Solution Approach 1:
The patent segments the data transfer path by creating dedicated direct memory channels between DRAM dies that bypass the custom logic die. Instead of routing all data through the custom die, separate TSV connections establish direct pathways between memory devices, dividing the system into independent communication channels that operate in parallel.
Solution Approach 2:
The patent introduces time-division multiplexing as an intermediary mechanism to manage shared TSV connections between DRAM dies. By allocating specific time slots for direct memory-to-memory communication, the system enables efficient data transfer without requiring dedicated physical channels for every possible connection, thus reducing overall system complexity while maintaining low latency.
2Productivity
If direct memory channels are implemented between DRAM dies, then bandwidth increases and latency decreases, but device complexity increases
Solution Approach 1:
The patent merges multiple communication functions into shared TSV connections by implementing time-division multiplexing. Instead of creating separate dedicated channels for each DRAM die pair, the system combines data transfer, address, and control signals into shared physical pathways that are allocated to different die pairs at different time slots, thereby increasing bandwidth without proportionally increasing structural complexity.
Solution Approach 2:
The TSV connections in the patent serve multiple functions: they can be used for traditional I/O operations through the custom logic die, for direct memory-to-memory data transfer, and for address and control signal transmission. This multi-functionality allows the same physical infrastructure to support high-bandwidth direct access while maintaining compatibility with existing memory controller architectures.
3Productivity
If time-division multiplexing is used for direct memory access, then data transfer efficiency improves, but control complexity increases
Solution Approach 1:
The patent implements a self-service mechanism where DRAM dies autonomously monitor and respond to time slot allocations for direct access operations. Each die can independently initiate data transfer during its allocated time slots without requiring continuous controller intervention, thereby improving transfer efficiency while reducing the control complexity burden on the memory controller.
Data Source
AI summary
An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also has one or more custom logic, controller, or processor die. The custom die(s) of the stack include direct channel interfaces that allow direct access to memory regions on one or more DRAMs in the stack. The direct channels are time-division multiplexed such that each DRAM die is associated with a time slot on a direct channel. The custom die configures a first DRAM die to read a block of data and transmit it via the direct channel using a time slot that is assigned to a second DRAM die. The custom die also configures the second memory device to receive the first block of data in its assigned time slot and write the block of data.